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powerpc_isa.cpp
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/**
* @file powerpc_isa.cpp
* @author Bruno Corsi dos Santos
*
* The ArchC Team
* http://www.archc.org/
*
* Computer Systems Laboratory (LSC)
* IC-UNICAMP
* http://www.lsc.ic.unicamp.br
*
* @version 1.0
* @date Mon, 19 Jun 2006 15:50:48 -0300
*
* @brief The ArchC POWERPC functional model.
*
* @attention Copyright (C) 2002-2006 --- The ArchC Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
//IMPLEMENTATION NOTES:
// PowerPC 32 bits family.
// The PowerPC 405 instruction family are not implemented.
// Based on IBM and Xilinx manuals of PowerPC 405.
// mtspr and mfspr instructions not completely implemented.
// sc instruction not completely implemented and never used.
#include "powerpc_isa.H"
#include "powerpc_isa_init.cpp"
#include "powerpc_bhv_macros.H"
//If you want debug information for this model, uncomment next line
//#define DEBUG_MODEL
#include "ac_debug_model.H"
#define DEFAULT_STACK_SIZE (512 * 1024)
static int processors_started = 0;
using namespace powerpc_parms;
#ifdef SLEEP_AWAKE_MODE
/*********************************************************************************/
/* SLEEP / AWAKE mode control */
/* INTR_REG may store 1 (AWAKE MODE) or 0 (SLEEP MODE) */
/* if intr_reg == 0, the simulator will be suspended until it receives a */
/* interruption 1 */
/*********************************************************************************/
#define test_sleep() { if (intr_reg.read() == 0) ac_wait(); }
#else
#define test_sleep() {}
#endif
//Compute CR0 fields LT, GT, EQ, SO
//XER.SO must be updated by instruction before the use of this routine!
//Arguments:
//int result -> The result register
inline void CR0_update(ac_reg<ac_word> &CR, ac_reg<ac_word> &XER, unsigned int result) {
/* LT field */
if((result & 0x80000000) >> 31)
CR.write(CR.read() | 0x80000000); /* 1 */
else
CR.write(CR.read() & 0x7FFFFFFF); /* 0 */
/* GT field */
if(((~result & 0x80000000) >> 31) && (result!=0))
CR.write(CR.read() | 0x40000000); /* 1 */
else
CR.write(CR.read() & 0xBFFFFFFF); /* 0 */
/* EQ field */
if(result==0)
CR.write(CR.read() | 0x20000000); /* 1 */
else
CR.write(CR.read() & 0xDFFFFFFF); /* 0 */
/* SO field */
if(XER.read() & 0x80000000)
CR.write(CR.read() | 0x10000000); /* 1 */
else
CR.write(CR.read() & 0xEFFFFFFF); /* 0 */
}
//Compute XER overflow fields SO, OV
//Arguments:
//int result -> The result register
//int s1 -> Source 1
//int s2 -> Source 2
//int s3 -> Source 3 (if only two sources, use 0)
inline void add_XER_OV_SO_update(ac_reg<ac_word> &XER, int result,int s1,int s2,int s3) {
long long int longresult =
(long long int)(int)s1 + (long long int)(int)s2 + (long long int)(int)s3;
if(longresult != (long long int)(int)result) {
XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */
XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */
}
else {
XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */
}
}
//Compute XER carry field CA
//Arguments:
//int result -> The result register
//int s1 -> Source 1
//int s2 -> Source 2
//int s3 -> Source 3 (if only two sources, use 0)
inline void add_XER_CA_update(ac_reg<ac_word> &XER, int result,int s1,int s2,int s3) {
unsigned long long int longresult =
(unsigned long long int)(unsigned int)s1 +
(unsigned long long int)(unsigned int)s2 +
(unsigned long long int)(unsigned int)s3;
if(longresult > 0xFFFFFFFF)
XER.write(XER.read() | 0x20000000); /* Write 1 to bit 2 CA */
else
XER.write(XER.read() & 0xDFFFFFFF); /* Write 0 to bit 2 CA */
}
//Compute XER overflow fields SO, OV
//Arguments:
//int result -> The result register
//int s1 -> Source 1
//int s2 -> Source 2
inline void divws_XER_OV_SO_update(ac_reg<ac_word> &XER, int result,int s1,int s2) {
long long int longresult =
(long long int)(int)s1 / (long long int)(int)s2;
if(longresult != (long long int)(int)result) {
XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */
XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */
}
else
XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */
}
//Compute XER overflow fields SO, OV
//Arguments:
//int result -> The result register
//int s1 -> Source 1
//int s2 -> Source 2
inline void divwu_XER_OV_SO_update(ac_reg<ac_word> &XER, int result,int s1,int s2) {
unsigned long long int longresult =
(unsigned long long int)(unsigned int)s1 /
(unsigned long long int)(unsigned int)s2;
if(longresult != (unsigned long long int)(unsigned int)result) {
XER.write(XER.read() | 0x40000000); /* Write 1 to bit 1 OV */
XER.write(XER.read() | 0x80000000); /* Write 1 to bit 0 SO */
}
else
XER.write(XER.read() & 0xBFFFFFFF); /* Write 0 to bit 1 OV */
}
//Function to do_branch
inline void do_Branch(ac_reg<ac_word> &ac_pc, ac_reg<ac_word> &LR, signed int ili,unsigned int iaa,unsigned int ilk) {
int displacement;
unsigned int nia;
ac_pc-=4; /* Because pre-increment */
if(iaa==1) {
displacement=ili<<2;
nia=displacement;
}
else { /* iaa=0 */
displacement=ili<<2;
nia=ac_pc+displacement;
}
if(ilk==1)
LR.write(ac_pc+4);
ac_pc=nia;
}
//Function to do conditional branch
inline void do_Branch_Cond(ac_reg<ac_word> &ac_pc, ac_reg<ac_word> &LR, ac_reg<ac_word> &CR, ac_reg<ac_word> &CTR, unsigned int ibo,unsigned int ibi,
signed int ibd,unsigned int iaa,
unsigned int ilk) {
int displacement;
unsigned int nia;
unsigned int masc;
masc=0x80000000;
masc=masc>>ibi;
ac_pc-=4; /* Because pre-increment */
if((ibo & 0x04) == 0x00) {
CTR.write(CTR.read()-1);
}
if(((ibo & 0x04) || /* Branch */
((CTR.read()==0) && (ibo & 0x02)) ||
(!(CTR.read()==0) && !(ibo & 0x02)))
&&
((ibo & 0x10) ||
(((CR.read() & masc) && (ibo & 0x08)) ||
(!(CR.read() & masc) && !(ibo & 0x08))))) {
if(iaa == 1) {
displacement=ibd<<2;
nia=displacement;
}
else {
displacement=ibd<<2;
nia=ac_pc+displacement;
}
}
else { /* No branch */
nia=ac_pc+4;
}
if(ilk==1)
LR.write(ac_pc+4);
ac_pc=nia;
}
//Function to do conditional branch to count register
inline void do_Branch_Cond_Count_Reg(ac_reg<ac_word> &ac_pc, ac_reg<ac_word> &LR, ac_reg<ac_word> &CR, ac_reg<ac_word> &CTR, unsigned int ibo, unsigned int ibi,
unsigned int ilk) {
unsigned int nia;
unsigned int masc;
masc=0x80000000;
masc=masc>>ibi;
ac_pc-=4; /* Because pre-increment */
if((ibo & 0x04) == 0x00)
CTR.write(CTR.read()-1);
if(((ibo & 0x04) || /* Branch */
((CTR.read()==0) && (ibo & 0x02)) ||
(!(CTR.read()==0) && !(ibo & 0x02)))
&&
((ibo & 0x10) ||
(((CR.read() & masc) && (ibo & 0x08)) ||
(!(CR.read() & masc) && !(ibo & 0x08))))) {
nia=CTR.read() & 0xFFFFFFFC;
}
else { /* No Branch */
nia=ac_pc+4;
}
if(ilk==1)
LR.write(ac_pc+4);
ac_pc=nia;
}
//Function to do conditional branch to link register
inline void do_Branch_Cond_Link_Reg(ac_reg<ac_word> &ac_pc, ac_reg<ac_word> &LR, ac_reg<ac_word> &CR, ac_reg<ac_word> &CTR,unsigned int ibo,unsigned int ibi,
unsigned int ilk) {
unsigned int nia;
unsigned int masc;
masc=0x80000000;
masc=masc>>ibi;
ac_pc-=4; /* Because pre-increment */
if((ibo & 0x04) == 0x00)
CTR.write(CTR.read()-1);
if(((ibo & 0x04) || /* Branch */
((CTR.read()==0) && (ibo & 0x02)) ||
(!(CTR.read()==0) && !(ibo & 0x02)))
&&
((ibo & 0x10) ||
(((CR.read() & masc) && (ibo & 0x08)) ||
(!(CR.read() & masc) && !(ibo & 0x08))))) {
nia=LR.read() & 0xFFFFFFFC;
}
else { /* No Branch */
nia=ac_pc+4;
}
if(ilk==1)
LR.write(ac_pc+4);
ac_pc=nia;
}
#ifdef AC_COMPSIM
//Function to test if conditional branch is taken
int test_Branch_Cond(ac_reg<ac_word> &CR, ac_reg<ac_word> &CTR, unsigned int ibo, unsigned int ibi) {
unsigned int masc;
unsigned int test;
masc=0x80000000;
masc=masc>>ibi;
if((ibo & 0x04) == 0x00)
CTR.write(CTR.read()-1);
if(((ibo & 0x04) || /* Branch */
((CTR.read()==0) && (ibo & 0x02)) ||
(!(CTR.read()==0) && !(ibo & 0x02)))
&&
((ibo & 0x10) ||
(((CR.read() & masc) && (ibo & 0x08)) ||
(!(CR.read() & masc) && !(ibo & 0x08)))))
return 1;
else /* No Branch */
return 0;
}
#endif
//Ceil function
inline int ceil(int value, int divisor) {
int res;
if ((value % divisor)!=0)
res=int(value/divisor)+1;
else res=value/divisor;
return res;
}
//Rotl function
inline unsigned int rotl(unsigned int reg,unsigned int n) {
unsigned int tmp1=reg;
unsigned int tmp2=reg;
unsigned int rotated=(tmp1 << n) | (tmp2 >> (32-n));
return(rotated);
}
//Mask32rlw function
inline unsigned int mask32rlw(unsigned int i,unsigned int f) {
unsigned int maski,maskf;
if(i<=f) {
maski=(0xFFFFFFFF>>i);
maskf=(0xFFFFFFFF<<(31-f));
return(maski & maskf);
}
else {
maski=(0xFFFFFFFF>>f);
maski=maski>>1;
maskf=(0xFFFFFFFF<<(31-i));
maskf=maskf<<1;
return(~(maski & maskf));
}
}
//Function dump General Purpose Registers
inline void dumpGPR(ac_regbank<32, ac_word, ac_Dword> &GPR) {
int i;
for(i=0 ; i<32 ; i++)
dbg_printf("r%d -> %#x \n",i,GPR.read(i));
}
//Function that returns the value of XER TBC
inline unsigned int XER_TBC_read(ac_reg<ac_word> &XER) {
return(XER.read() & 0x0000007F);
}
//Function that returns the value of XER OV
inline unsigned int XER_OV_read(ac_reg<ac_word> &XER) {
if(XER.read() & 0x40000000)
return 1;
else
return 0;
}
//Function that returns the value of XER SO
inline unsigned int XER_SO_read(ac_reg<ac_word> &XER) {
if(XER.read() & 0x80000000)
return 1;
else
return 0;
}
//Function that returns the value of XER CA
inline unsigned int XER_CA_read(ac_reg<ac_word> &XER) {
if(XER.read() & 0x20000000)
return 1;
else
return 0;
}
//Function dump various registers
inline void dumpREG(ac_reg<ac_word> &XER, ac_reg<ac_word> &CR, ac_reg<ac_word> &LR, ac_reg<ac_word> &CTR) {
dbg_printf("XER.OV = %d\n",XER_OV_read(XER));
dbg_printf("XER.SO = %d\n",XER_SO_read(XER));
dbg_printf("XER.CA = %d\n",XER_CA_read(XER));
dbg_printf("CR = %#x\n",CR.read());
dbg_printf("LR = %#x\n",LR.read());
dbg_printf("CTR = %#x\n",CTR.read());
}
//!Generic instruction behavior method.
void ac_behavior( instruction )
{
test_sleep();
dbg_printf("\n program counter=%#x\n",(int)ac_pc);
ac_pc+=4;
//dumpGPR();
//dumpREG();
}
//!Generic begin behavior method.
void ac_behavior( begin )
{
dbg_printf("Starting simulator...\n");
/* Here the stack is started in a */
// GPR.write(1,AC_RAM_END - 1024);
GPR.write(1, AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE);
/* Make a jump out of DC_portory if it doesn't have an abi */
LR.write(0xFFFFFFFF);
}
void ac_behavior(end)
{
dbg_printf("@@@ end behavior @@@\n");
}
//! Instruction Format behavior methods.
void ac_behavior( I1 ){}
void ac_behavior( B1 ){}
void ac_behavior( SC1 ){}
void ac_behavior( D1 ){}
void ac_behavior( D2 ){}
void ac_behavior( D3 ){}
void ac_behavior( D4 ){}
void ac_behavior( D5 ){}
void ac_behavior( D6 ){}
void ac_behavior( D7 ){}
void ac_behavior( X1 ){}
void ac_behavior( X2 ){}
void ac_behavior( X3 ){}
void ac_behavior( X4 ){}
void ac_behavior( X5 ){}
void ac_behavior( X6 ){}
void ac_behavior( X7 ){}
void ac_behavior( X8 ){}
void ac_behavior( X9 ){}
void ac_behavior( X10 ){}
void ac_behavior( X11 ){}
void ac_behavior( X12 ){}
void ac_behavior( X13 ){}
void ac_behavior( X14 ){}
void ac_behavior( X15 ){}
void ac_behavior( X16 ){}
void ac_behavior( X17 ){}
void ac_behavior( X18 ){}
void ac_behavior( X19 ){}
void ac_behavior( X20 ){}
void ac_behavior( X21 ){}
void ac_behavior( X22 ){}
void ac_behavior( X23 ){}
void ac_behavior( X24 ){}
void ac_behavior( X25 ){}
void ac_behavior( XL1 ){}
void ac_behavior( XL2 ){}
void ac_behavior( XL3 ){}
void ac_behavior( XL4 ){}
void ac_behavior( XFX1 ){}
void ac_behavior( XFX2 ){}
void ac_behavior( XFX3 ){}
void ac_behavior( XFX4 ){}
void ac_behavior( XFX5 ){}
void ac_behavior( XO1 ){}
void ac_behavior( XO2 ){}
void ac_behavior( XO3 ){}
void ac_behavior( M1 ){}
void ac_behavior( M2 ){}
//!Instruction add behavior method.
void ac_behavior( add )
{
dbg_printf(" add r%d, r%d, r%d\n\n",rt,ra,rb);
GPR.write(rt,GPR.read(ra) + GPR.read(rb));
};
//!Instruction add_ behavior method.
void ac_behavior( add_ )
{
dbg_printf(" add. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addo behavior method.
void ac_behavior( addo )
{
dbg_printf(" addo r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0);
GPR.write(rt,result);
};
//!Instruction addo_ behavior method.
void ac_behavior( addo_ )
{
dbg_printf(" addo. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
/* Note: XER_OV_SO_update before CR0_update */
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addc behavior method.
void ac_behavior( addc )
{
dbg_printf(" addc r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0);
GPR.write(rt,result);
};
//!Instruction addc_ behavior method.
void ac_behavior( addc_ )
{
dbg_printf(" addc. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0);
CR0_update(CR, XER, result);
};
//!Instruction addco behavior method.
void ac_behavior( addco )
{
dbg_printf(" addco r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0);
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0);
GPR.write(rt,result);
};
//!Instruction addco_ behavior method.
void ac_behavior( addco_ )
{
dbg_printf(" addco. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),0);
/* Note: XER_OV_SO_update before CR0_update */
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),0);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction adde behavior method.
void ac_behavior( adde )
{
dbg_printf(" adde r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
GPR.write(rt,result);
};
//!Instruction adde_ behavior method.
void ac_behavior( adde_ )
{
dbg_printf(" adde. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addeo behavior method.
void ac_behavior( addeo )
{
dbg_printf(" addeo r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
GPR.write(rt,result);
};
//!Instruction addeo_ behavior method.
void ac_behavior( addeo_ )
{
dbg_printf(" addeo. r%d, r%d, r%d\n\n",rt,ra,rb);
int result=GPR.read(ra) + GPR.read(rb) + XER_CA_read(XER);
add_XER_CA_update(XER, GPR.read(rt),GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
/* Note: XER_OV_SO_update before CR0_update */
add_XER_OV_SO_update(XER, result,GPR.read(ra),GPR.read(rb),XER_CA_read(XER));
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addi behavior method.
void ac_behavior( addi )
{
dbg_printf(" addi r%d, r%d, %d\n\n",rt,ra,d);
int ime32=d;
if(ra == 0)
GPR.write(rt,ime32);
else
GPR.write(rt,GPR.read(ra)+ime32);
};
//!Instruction addic behavior method.
void ac_behavior( addic )
{
dbg_printf(" addic r%d, r%d, %d\n\n",rt,ra,d);
int ime32=d;
int result=GPR.read(ra)+ime32;
add_XER_CA_update(XER, result,GPR.read(ra),ime32,0);
GPR.write(rt,result);
};
//!Instruction addic_ behavior method.
void ac_behavior( addic_ )
{
dbg_printf(" addic. r%d, r%d, %d\n\n",rt,ra,d);
/* Do not have rc field and update CR0 */
int ime32=d;
int result=GPR.read(ra)+ime32;
add_XER_CA_update(XER, result,GPR.read(ra),ime32,0);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addis behavior method.
void ac_behavior( addis )
{
dbg_printf(" addis r%d, r%d, %d\n\n",rt,ra,d);
int ime32=d;
ime32=ime32<<16;
if(ra == 0)
GPR.write(rt,ime32);
else
GPR.write(rt,GPR.read(ra)+ime32);
};
//!Instruction addme behavior method.
void ac_behavior( addme )
{
dbg_printf(" addme r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER)+(-1);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
GPR.write(rt,result);
};
//!Instruction addme_ behavior method.
void ac_behavior( addme_ )
{
dbg_printf(" addme. r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER)+(-1);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addmeo behavior method.
void ac_behavior( addmeo )
{
dbg_printf(" addmeo r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER)+(-1);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
GPR.write(rt,result);
};
//!Instruction addmeo_ behavior method.
void ac_behavior( addmeo_ )
{
dbg_printf(" addmeo. r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER)+(-1);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
/* Note: XER_OV_SO_update before CR0_update */
add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),-1);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addze behavior method.
void ac_behavior( addze )
{
dbg_printf(" addze r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
GPR.write(rt,result);
};
//!Instruction addze_ behavior method.
void ac_behavior( addze_ )
{
dbg_printf(" addze. %d, %d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction addzeo behavior method.
void ac_behavior( addzeo )
{
dbg_printf(" addzeo r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
GPR.write(rt,result);
};
//!Instruction addzeo_ behavior method.
void ac_behavior( addzeo_ )
{
dbg_printf(" addzeo. r%d, r%d\n\n",rt,ra);
int result=GPR.read(ra)+XER_CA_read(XER);
add_XER_CA_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
/* Note: XER_OV_SO_update before CR0_update */
add_XER_OV_SO_update(XER, result,GPR.read(ra),XER_CA_read(XER),0);
CR0_update(CR, XER, result);
GPR.write(rt,result);
};
//!Instruction ande behavior method.
void ac_behavior( ande )
{
dbg_printf(" and r%d, r%d, r%d\n\n",ra,rs,rb);
GPR.write(ra,GPR.read(rs) & GPR.read(rb));
};
//!Instruction ande_ behavior method.
void ac_behavior( ande_ )
{
dbg_printf(" and. r%d, r%d, r%d\n\n",ra,rs,rb);
int result=GPR.read(rs) & GPR.read(rb);
CR0_update(CR, XER, result);
GPR.write(ra,result);
};
//!Instruction andc behavior method.
void ac_behavior( andc )
{
dbg_printf(" andc r%d, r%d, r%d\n\n",ra,rs,rb);
GPR.write(ra,GPR.read(rs) & ~GPR.read(rb));
};
//!Instruction ande_ behavior method.
void ac_behavior( andc_ )
{
dbg_printf(" andc. r%d, r%d, r%d\n\n",ra,rs,rb);
int result=GPR.read(rs) & ~GPR.read(rb);
CR0_update(CR, XER, result);
GPR.write(ra,result);
};
//!Instruction andi_ behavior method.
void ac_behavior( andi_ )
{
dbg_printf(" andi. r%d, r%d, %d\n\n",ra,rs,ui);
unsigned int ime32=(unsigned short int)ui;
int result=GPR.read(rs) & ime32;
CR0_update(CR, XER, result);
GPR.write(ra,result);
};
//!Instruction andis_ behavior method.
void ac_behavior( andis_ )
{
dbg_printf(" andis. r%d, r%d, %d\n\n",ra,rs,ui);
unsigned int ime32=(unsigned short int)ui;
ime32=ime32<<16;
int result=GPR.read(rs) & ime32;
CR0_update(CR, XER, result);
GPR.write(ra,result);
};
//!Instruction b behavior method.
void ac_behavior( b )
{
dbg_printf(" b %d\n\n",li);
do_Branch(ac_pc, LR, li,aa,lk);
};
//!Instruction ba behavior method.
void ac_behavior( ba )
{
dbg_printf(" ba %d\n\n",li);
do_Branch(ac_pc, LR, li,aa,lk);
};
//!Instruction bl behavior method.
void ac_behavior( bl )
{
dbg_printf(" bl %d\n\n",li);
do_Branch(ac_pc, LR, li,aa,lk);
};
//!Instruction bla behavior method.
void ac_behavior( bla )
{
dbg_printf(" bla %d\n\n",li);
do_Branch(ac_pc, LR, li,aa,lk);
};
//!Instruction bc behavior method.
void ac_behavior( bc )
{
dbg_printf(" bc %d, %d, %d\n\n",bo,bi,bd);
do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk);
};
//!Instruction bca behavior method.
void ac_behavior( bca )
{
dbg_printf(" bca %d, %d, %d\n\n",bo,bi,bd);
do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk);
};
//!Instruction bcl behavior method.
void ac_behavior( bcl )
{
dbg_printf(" bcl %d, %d, %d\n\n",bo,bi,bd);
do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk);
};
//!Instruction bcla behavior method.
void ac_behavior( bcla )
{
dbg_printf(" bcla %d, %d, %d\n\n",bo,bi,bd);
do_Branch_Cond(ac_pc, LR, CR, CTR, bo,bi,bd,aa,lk);
};
//!Instruction bcctr behavior method.
void ac_behavior( bcctr )
{
dbg_printf(" bcctr %d, %d\n\n",bo,bi);
do_Branch_Cond_Count_Reg(ac_pc, LR, CR, CTR,bo,bi,lk);
};
//!Instruction bcctrl behavior method.
void ac_behavior( bcctrl )
{
dbg_printf(" bcctrl %d, %d\n\n",bo,bi);
do_Branch_Cond_Count_Reg(ac_pc, LR, CR, CTR,bo,bi,lk);
};
//!Instruction bclr behavior method.
void ac_behavior( bclr )
{
dbg_printf(" bclr %d, %d\n\n",bo,bi);
do_Branch_Cond_Link_Reg(ac_pc, LR, CR, CTR,bo,bi,lk);
};
//!Instruction bclrl behavior method.
void ac_behavior( bclrl )
{
dbg_printf(" bclrl %d, %d\n\n",bo,bi);
do_Branch_Cond_Link_Reg(ac_pc, LR, CR, CTR,bo,bi,lk);
};
//!Instruction cmp behavior method.
void ac_behavior( cmp )
{
dbg_printf(" cmp crf%d, 0, r%d, r%d\n\n",bf,ra,rb);
unsigned int c=0x00;