From da756cb316c501e8fe68ba03688fc069c7d0ce4a Mon Sep 17 00:00:00 2001 From: Carlos Venegas Date: Sun, 12 Jan 2025 01:43:30 +0100 Subject: [PATCH] Fix Alhambra-II test lint errors --- apio/managers/scons.py | 1 - .../icestudio-jumping-led/02-jumping-LED.ice | 24 +- .../02-jumping-LED_tb.gtkw | 40 +- .../icestudio-jumping-led/02-jumping-LED_tb.v | 41 +- .../icestudio-jumping-led/main.pcf | 2 +- .../alhambra-ii/icestudio-jumping-led/main.v | 431 +++++++------- .../alhambra-ii/icestudio-ledon/ledon_tb.gtkw | 23 +- .../alhambra-ii/icestudio-ledon/ledon_tb.v | 13 +- .../alhambra-ii/icestudio-ledon/main.pcf | 2 +- .../ice40/alhambra-ii/icestudio-ledon/main.v | 9 +- .../01-LEDs-buttons_tb.gtkw | 4 +- .../01-LEDs-buttons_tb.v | 54 +- .../icestudio-leds-buttons/main.pcf | 2 +- .../alhambra-ii/icestudio-leds-buttons/main.v | 7 +- .../03-riscv-stop-watch.ice | 153 ++++- .../03-riscv-stop-watch_tb.gtkw | 33 +- .../03-riscv-stop-watch_tb.v | 28 +- .../icestudio-riscv-stop-watch/main.pcf | 2 +- .../icestudio-riscv-stop-watch/main.v | 528 +++++++++--------- .../ice40/alhambra-ii/icestudio-tff/main.pcf | 3 +- .../ice40/alhambra-ii/icestudio-tff/main.v | 121 +--- .../alhambra-ii/icestudio-tff/tff_tb.gtkw | 29 +- .../ice40/alhambra-ii/icestudio-tff/tff_tb.v | 26 +- 23 files changed, 792 insertions(+), 784 deletions(-) diff --git a/apio/managers/scons.py b/apio/managers/scons.py index 7c02df59..801a5dfa 100644 --- a/apio/managers/scons.py +++ b/apio/managers/scons.py @@ -946,4 +946,3 @@ def _run( # -- Return the exit code return result.exit_code - diff --git a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED.ice b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED.ice index 71ed64e8..8ef62367 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED.ice +++ b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED.ice @@ -3052,7 +3052,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "//-- Initial value\nreg q = INI;\n\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n q <= d;", + "code": "//-- Initial value\nreg qi = INI;\nassign q = qi;\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n qi <= d;", "params": [ { "name": "INI" @@ -3800,8 +3800,8 @@ "clock": false }, "position": { - "x": 72, - "y": 256 + "x": -16, + "y": 360 } }, { @@ -3811,8 +3811,8 @@ "name": "" }, "position": { - "x": 704, - "y": 256 + "x": 912, + "y": 360 } }, { @@ -3824,15 +3824,15 @@ "local": false }, "position": { - "x": 408, - "y": -8 + "x": 448, + "y": -88 } }, { "id": "2b245a71-2d80-466b-955f-e3d61839fe25", "type": "basic.code", "data": { - "code": "// 1-Pull up\n\n//-- Place the IO block, configured as \n//-- input with pull-up\nSB_IO\n #(\n .PIN_TYPE(6'b 1010_01),\n \n //-- The pull-up is activated or not\n //-- depeding on the ON parameter\n .PULLUP(ON)\n \n ) input_pin (\n\n //--- Input pin\n .PACKAGE_PIN(i),\n \n //-- Block output\n .D_IN_0(o),\n \n //-- Configured as input\n .OUTPUT_ENABLE(1'b0),\n \n //-- Not used\n .D_OUT_0(1'b0)\n );", + "code": "// 1-Pull up\n\nwire pin_i;\nassign pin_i=i;\nwire unused_d_in_1;\n\n//-- Place the IO block, configured as \n//-- input with pull-up\nSB_IO\n #(\n .PIN_TYPE(6'b1010_01),\n \n //-- The pull-up is activated or not\n //-- depeding on the ON parameter\n .PULLUP(ON)\n \n ) input_pin (\n\n //--- Input pin\n .PACKAGE_PIN(pin_i),\n \n //-- Block output\n .D_IN_0(o),\n \n //-- Configured as input\n .OUTPUT_ENABLE(1'b0),\n \n //-- Not used\n .D_IN_1(unused_d_in_1),\n .D_OUT_0(1'b0),\n .D_OUT_1(1'b0),\n .OUTPUT_CLK(1'b0),\n .INPUT_CLK(1'b0),\n .LATCH_INPUT_VALUE(1'b0), \n .CLOCK_ENABLE(1'b0) \n );", "params": [ { "name": "ON" @@ -3856,8 +3856,8 @@ "y": 104 }, "size": { - "width": 392, - "height": 368 + "width": 480, + "height": 576 } }, { @@ -4468,7 +4468,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "reg q = INI;\n\nalways @(posedge clk)\n if (load)\n q <= d;", + "code": "reg qi = INI;\nassign q = qi;\nalways @(posedge clk)\n if (load)\n qi <= d;", "params": [ { "name": "INI" @@ -20223,7 +20223,7 @@ "id": "32106310-bfdc-41db-9a7c-2dadd5016c3f", "type": "basic.code", "data": { - "code": "localparam N = 8;\n\nreg [N-1:0] q = INI;\n\nalways @(posedge clk)\n if (load)\n q <= d;", + "code": "localparam N = 8;\n\nreg [N-1:0] qi = INI;\n\nalways @(posedge clk)\n if (load)\n qi <= d;\n \nassign q = qi;", "params": [ { "name": "INI" diff --git a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.gtkw b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.gtkw index dd21b25f..1e4d6594 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.gtkw +++ b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.gtkw @@ -1,37 +1,5 @@ -[*] -[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Thu Apr 28 10:41:03 2022 -[*] -[dumpfile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/alhambra-ii/02-jumping-LED/02-jumping-LED_tb.vcd" -[dumpfile_mtime] "Thu Apr 28 10:38:49 2022" -[dumpfile_size] 739918 -[savefile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/alhambra-ii/02-jumping-LED/02-jumping-LED_tb.gtkw" -[timestart] 0 -[size] 1860 1016 -[pos] 60 27 -*-17.076054 10000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[sst_width] 233 -[signals_width] 112 -[sst_expanded] 1 -[sst_vpaned_height] 288 -@29 -main_tb.clk -@800022 +[*] Code generated by Icestudio 0.13.2w202501120101 +[*] Sun, 12 Jan 2025 00:12:05 GMT + +main_tb.Botón main_tb.LED[7:0] -@28 -(0)main_tb.LED[7:0] -(1)main_tb.LED[7:0] -(2)main_tb.LED[7:0] -(3)main_tb.LED[7:0] -(4)main_tb.LED[7:0] -(5)main_tb.LED[7:0] -(6)main_tb.LED[7:0] -(7)main_tb.LED[7:0] -@1001200 --group_end -@200 -- -@28 -main_tb.Boton -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.v b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.v index 2c6ebbf0..37e8f80b 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.v +++ b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/02-jumping-LED_tb.v @@ -1,9 +1,15 @@ -// Code generated by Icestudio 0.9.2w202204260904 -// Thu, 28 Apr 2022 10:23:57 GMT +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules +// Sun, 12 Jan 2025 00:11:49 GMT // Testbench template `default_nettype none +`define DUMPSTR(x) `"x.vcd`" `timescale 10 ns / 1 ns @@ -11,34 +17,37 @@ module main_tb ; // Simulation time: 100ns (10 * 10ns) - parameter DURATION = 400; + parameter DURATION = 10; + + // TODO: edit the module parameters here + // e.g. localparam constant_value = 1; + localparam constant_Divisor = 240000; + localparam constant_vel_ini = 25; + localparam constant_acel_ini = -2; -//-- Clock signal -reg clk = 0; -always #0.5 clk = ~clk; - // Input/Output - reg Boton; - + reg Botón; wire [7:0] LED; // Module instance - main MAIN ( - .vclk(clk), - .v68e749(Boton), + main #( + .v98ea37(constant_Divisor), + .v315560(constant_vel_ini), + .v0f02ae(constant_acel_ini) + ) MAIN ( + .v68e749(Botón), .vb5f8d6(LED) ); initial begin - // Dump vars to the output .vcd file + // File were to store the simulation results + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); $dumpvars(0, main_tb); // TODO: initialize the registers here // e.g. value = 1; // e.g. #2 value = 0; - Boton = 0; - - #1 Boton=1; + Botón = 0; #(DURATION) $display("End of simulation"); $finish; diff --git a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.pcf b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.pcf index fa9d404a..89025330 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.pcf +++ b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.pcf @@ -1,4 +1,4 @@ -# Code generated by Icestudio 0.8.1w202112300112 +# Code generated by Icestudio 0.13.2w202501120101 set_io vb5f8d6[7] 37 set_io vb5f8d6[6] 38 diff --git a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.v b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.v index 5951219f..18390aa2 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.v +++ b/test-examples/ice40/alhambra-ii/icestudio-jumping-led/main.v @@ -1,4 +1,9 @@ -// Code generated by Icestudio 0.8.1w202112300112 +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules `default_nettype none @@ -15,17 +20,17 @@ module main #( localparam p3 = v98ea37; localparam p7 = v0f02ae; localparam p10 = v315560; - wire [0:7] w0; + wire [7:0] w0; wire w1; wire w2; - wire [0:2] w4; - wire [0:7] w5; - wire [0:7] w6; - wire [0:7] w8; + wire [2:0] w4; + wire [7:0] w5; + wire [7:0] w6; + wire [7:0] w8; wire w9; - wire [0:7] w11; - wire [0:7] w12; - wire [0:7] w13; + wire [7:0] w11; + wire [7:0] w12; + wire [7:0] w13; wire w14; wire w15; wire w16; @@ -38,21 +43,21 @@ module main #( wire w23; wire w24; wire w25; - wire [0:7] w26; + wire [7:0] w26; wire w27; wire w28; - wire [0:7] w29; - wire [0:7] w30; + wire [7:0] w29; + wire [7:0] w30; wire w31; wire w32; wire w33; wire w34; wire w35; wire w36; - wire [0:7] w37; - wire [0:7] w38; - wire [0:7] w39; - wire [0:7] w40; + wire [7:0] w37; + wire [7:0] w38; + wire [7:0] w39; + wire [7:0] w40; assign vb5f8d6 = w0; assign w2 = v68e749; assign w20 = vclk; @@ -208,8 +213,8 @@ module v75c864 ( output [7:0] va8064a ); wire w0; - wire [0:7] w1; - wire [0:2] w2; + wire [7:0] w1; + wire [2:0] w2; assign w0 = v5a2634; assign va8064a = w1; assign w2 = v1336f1; @@ -380,13 +385,13 @@ module v053dc2_vb8adf8 #( output q ); //-- Initial value - reg q = INI; - + reg qi = INI; + assign q = qi; //-- Capture the input data //-- on the rising edge of //-- the system clock always @(posedge clk) - q <= d; + qi <= d; endmodule //---- Top entity module v3676a0 ( @@ -540,11 +545,15 @@ module v6c3aff_v34955f #( ); // 1-Pull up + wire pin_i; + assign pin_i=i; + wire unused_d_in_1; + //-- Place the IO block, configured as //-- input with pull-up SB_IO #( - .PIN_TYPE(6'b 1010_01), + .PIN_TYPE(6'b1010_01), //-- The pull-up is activated or not //-- depeding on the ON parameter @@ -553,7 +562,7 @@ module v6c3aff_v34955f #( ) input_pin ( //--- Input pin - .PACKAGE_PIN(i), + .PACKAGE_PIN(pin_i), //-- Block output .D_IN_0(o), @@ -562,7 +571,13 @@ module v6c3aff_v34955f #( .OUTPUT_ENABLE(1'b0), //-- Not used - .D_OUT_0(1'b0) + .D_IN_1(unused_d_in_1), + .D_OUT_0(1'b0), + .D_OUT_1(1'b0), + .OUTPUT_CLK(1'b0), + .INPUT_CLK(1'b0), + .LATCH_INPUT_VALUE(1'b0), + .CLOCK_ENABLE(1'b0) ); endmodule //---- Top entity @@ -654,11 +669,11 @@ module v93adf6_vb8adf8 #( input load, output q ); - reg q = INI; - + reg qi = INI; + assign q = qi; always @(posedge clk) if (load) - q <= d; + qi <= d; endmodule //---- Top entity module v413e4a ( @@ -668,10 +683,10 @@ module v413e4a ( output ve37344 ); wire w0; - wire [0:15] w1; - wire [0:15] w2; + wire [15:0] w1; + wire [15:0] w2; wire w3; - wire [0:15] w4; + wire [15:0] w4; wire w5; assign w0 = ve556f1; assign w3 = v6dda25; @@ -703,16 +718,16 @@ module vbc711b ( input [15:0] vc320da, output [15:0] v3f90b8 ); - wire [0:15] w0; - wire [0:15] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:3] w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; - wire [0:3] w8; - wire [0:3] w9; + wire [15:0] w0; + wire [15:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [3:0] w4; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; + wire [3:0] w8; + wire [3:0] w9; wire w10; wire w11; wire w12; @@ -801,8 +816,8 @@ module v5c75f6 ( wire w3; wire w4; wire w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -892,7 +907,7 @@ module vc4f23a ( wire w1; wire w2; wire w3; - wire [0:3] w4; + wire [3:0] w4; assign v3f8943 = w0; assign v64d863 = w1; assign vda577d = w2; @@ -937,7 +952,7 @@ module v84f0a1 ( wire w1; wire w2; wire w3; - wire [0:3] w4; + wire [3:0] w4; assign w0 = vee8a83; assign w1 = v03aaf0; assign w2 = vf8041d; @@ -1019,11 +1034,11 @@ module v852bc8 ( output [3:0] v71a717, output [3:0] v527ffb ); - wire [0:15] w0; - wire [0:3] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:3] w4; + wire [15:0] w0; + wire [3:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [3:0] w4; assign w0 = v91b9c1; assign v527ffb = w1; assign v71a717 = w2; @@ -1064,11 +1079,11 @@ module v401a28 ( input [3:0] vcc76e8, output [15:0] v14a530 ); - wire [0:15] w0; - wire [0:3] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:3] w4; + wire [15:0] w0; + wire [3:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [3:0] w4; assign v14a530 = w0; assign w1 = vcc76e8; assign w2 = vd531e6; @@ -1109,8 +1124,8 @@ module v8ecd59 #( ); localparam p1 = v6c5139; wire w0; - wire [0:15] w2; - wire [0:15] w3; + wire [15:0] w2; + wire [15:0] w3; assign v4642b6 = w0; assign w2 = v2f9d57; assign vd7988b = w3; @@ -1138,9 +1153,9 @@ module v265696 #( ); localparam p1 = vd73390; wire w0; - wire [0:15] w2; - wire [0:15] w3; - wire [0:15] w4; + wire [15:0] w2; + wire [15:0] w3; + wire [15:0] w4; assign v4642b6 = w0; assign w3 = v36f2dd; assign vc068fb = w4; @@ -1169,7 +1184,7 @@ module v651fa3 #( output [15:0] vcd9338 ); localparam p0 = vc5c8ea; - wire [0:15] w1; + wire [15:0] w1; assign vcd9338 = w1; v651fa3_v465065 #( .VALUE(p0) @@ -1200,15 +1215,15 @@ module vbc66d7 ( ); wire w0; wire w1; - wire [0:15] w2; - wire [0:15] w3; - wire [0:15] w4; - wire [0:7] w5; - wire [0:7] w6; - wire [0:7] w7; - wire [0:7] w8; - wire [0:7] w9; - wire [0:7] w10; + wire [15:0] w2; + wire [15:0] w3; + wire [15:0] w4; + wire [7:0] w5; + wire [7:0] w6; + wire [7:0] w7; + wire [7:0] w8; + wire [7:0] w9; + wire [7:0] w10; assign v4642b6 = w0; assign w2 = v603a9a; assign w3 = v1489e0; @@ -1254,9 +1269,9 @@ module v306ca3 ( output [7:0] vef5eee, output [7:0] vd3ef3b ); - wire [0:15] w0; - wire [0:7] w1; - wire [0:7] w2; + wire [15:0] w0; + wire [7:0] w1; + wire [7:0] w2; assign w0 = v91b9c1; assign vef5eee = w1; assign vd3ef3b = w2; @@ -1288,17 +1303,17 @@ module vcb23aa ( output v4642b6, output [7:0] v62bf25 ); - wire [0:7] w0; - wire [0:7] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:7] w4; + wire [7:0] w0; + wire [7:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [7:0] w4; wire w5; wire w6; - wire [0:3] w7; - wire [0:3] w8; - wire [0:3] w9; - wire [0:3] w10; + wire [3:0] w7; + wire [3:0] w8; + wire [3:0] w9; + wire [3:0] w10; assign w0 = veb2f59; assign w1 = v39966a; assign v62bf25 = w4; @@ -1344,9 +1359,9 @@ module v6bdcd9 ( output [3:0] v651522, output [3:0] v2cc41f ); - wire [0:3] w0; - wire [0:3] w1; - wire [0:7] w2; + wire [3:0] w0; + wire [3:0] w1; + wire [7:0] w2; assign v651522 = w0; assign v2cc41f = w1; assign w2 = vcc8c7c; @@ -1383,9 +1398,9 @@ module v25966b ( wire w2; wire w3; wire w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -1657,9 +1672,9 @@ module vafb28f ( input [3:0] v3c88fc, output [7:0] va9ac17 ); - wire [0:7] w0; - wire [0:3] w1; - wire [0:3] w2; + wire [7:0] w0; + wire [3:0] w1; + wire [3:0] w2; assign va9ac17 = w0; assign w1 = v515fe7; assign w2 = v3c88fc; @@ -1697,9 +1712,9 @@ module va1ce30 ( wire w2; wire w3; wire w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -1783,16 +1798,16 @@ module vc3c498 ( ); wire w0; wire w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:7] w4; - wire [0:3] w5; - wire [0:3] w6; + wire [7:0] w2; + wire [7:0] w3; + wire [7:0] w4; + wire [3:0] w5; + wire [3:0] w6; wire w7; - wire [0:3] w8; - wire [0:3] w9; - wire [0:3] w10; - wire [0:3] w11; + wire [3:0] w8; + wire [3:0] w9; + wire [3:0] w10; + wire [3:0] w11; assign w1 = vb9cfc3; assign w2 = v45c6ee; assign w3 = v20212e; @@ -1840,9 +1855,9 @@ module v8cc49c ( input [7:0] v2b8a97, output [15:0] v14a530 ); - wire [0:15] w0; - wire [0:7] w1; - wire [0:7] w2; + wire [15:0] w0; + wire [7:0] w1; + wire [7:0] w2; assign v14a530 = w0; assign w1 = v2b8a97; assign w2 = vb334ae; @@ -2001,8 +2016,8 @@ module vbce541 #( ); localparam p1 = va04f5d; wire w0; - wire [0:23] w2; - wire [0:23] w3; + wire [23:0] w2; + wire [23:0] w3; wire w4; wire w5; assign v4642b6 = w0; @@ -2037,7 +2052,7 @@ module vef98b5 #( output [23:0] ve70c2d ); localparam p0 = vc5c8ea; - wire [0:23] w1; + wire [23:0] w1; assign ve70c2d = w1; vef98b5_v465065 #( .VALUE(p0) @@ -2069,14 +2084,14 @@ module vd84ae0 ( wire w1; wire w2; wire w3; - wire [0:23] w4; - wire [0:23] w5; - wire [0:7] w6; - wire [0:7] w7; - wire [0:7] w8; - wire [0:7] w9; - wire [0:7] w10; - wire [0:7] w11; + wire [23:0] w4; + wire [23:0] w5; + wire [7:0] w6; + wire [7:0] w7; + wire [7:0] w8; + wire [7:0] w9; + wire [7:0] w10; + wire [7:0] w11; assign v4642b6 = w0; assign w4 = v06bdfb; assign w5 = va89056; @@ -2129,12 +2144,12 @@ module vb2762a ( wire w0; wire w1; wire w2; - wire [0:7] w3; - wire [0:7] w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; - wire [0:3] w8; + wire [7:0] w3; + wire [7:0] w4; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; + wire [3:0] w8; assign v4642b6 = w0; assign w3 = v715730; assign w4 = vf191e6; @@ -2177,8 +2192,8 @@ module v438230 ( output v4642b6 ); wire w0; - wire [0:3] w1; - wire [0:3] w2; + wire [3:0] w1; + wire [3:0] w2; wire w3; wire w4; wire w5; @@ -2353,10 +2368,10 @@ module v6fef69 ( output [7:0] v243fb2, output [7:0] va2a3a1 ); - wire [0:7] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:23] w3; + wire [7:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [23:0] w3; assign v243fb2 = w0; assign vd83cb2 = w1; assign va2a3a1 = w2; @@ -2393,10 +2408,10 @@ module v97d607 ( output ve37344 ); wire w0; - wire [0:23] w1; - wire [0:23] w2; + wire [23:0] w1; + wire [23:0] w2; wire w3; - wire [0:23] w4; + wire [23:0] w4; wire w5; assign w0 = ve556f1; assign w3 = v6dda25; @@ -2428,14 +2443,14 @@ module v5495b5 ( input [23:0] v15c6e6, output [23:0] vb02eea ); - wire [0:23] w0; - wire [0:23] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:7] w4; - wire [0:7] w5; - wire [0:7] w6; - wire [0:7] w7; + wire [23:0] w0; + wire [23:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [7:0] w4; + wire [7:0] w5; + wire [7:0] w6; + wire [7:0] w7; wire w8; wire w9; wire w10; @@ -2500,10 +2515,10 @@ module v33e50d ( input [7:0] v77c6e9, output [23:0] v6d326e ); - wire [0:23] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:7] w3; + wire [23:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [7:0] w3; assign v6d326e = w0; assign w1 = vf7d213; assign w2 = v77c6e9; @@ -2538,12 +2553,12 @@ module vcf4344 ( input [7:0] vd85d4e, output [7:0] vc1f0d2 ); - wire [0:3] w0; - wire [0:3] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:3] w4; - wire [0:3] w5; + wire [3:0] w0; + wire [3:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [3:0] w4; + wire [3:0] w5; wire w6; wire w7; wire w8; @@ -2595,8 +2610,8 @@ module v9c4559 #( ); localparam p1 = v6c5139; wire w0; - wire [0:23] w2; - wire [0:23] w3; + wire [23:0] w2; + wire [23:0] w3; assign v4642b6 = w0; assign w2 = v005b83; assign v53d485 = w3; @@ -2624,9 +2639,9 @@ module v44c099 #( ); localparam p1 = vd73390; wire w0; - wire [0:23] w2; - wire [0:23] w3; - wire [0:23] w4; + wire [23:0] w2; + wire [23:0] w3; + wire [23:0] w4; assign v4642b6 = w0; assign v8826c0 = w2; assign w3 = vd90f46; @@ -2655,7 +2670,7 @@ module v4c802f #( output [23:0] v8513f7 ); localparam p0 = vc5c8ea; - wire [0:23] w1; + wire [23:0] w1; assign v8513f7 = w1; v4c802f_v465065 #( .VALUE(p0) @@ -2685,23 +2700,23 @@ module v91404d ( output [23:0] vb5c06c ); wire w0; - wire [0:7] w1; - wire [0:7] w2; + wire [7:0] w1; + wire [7:0] w2; wire w3; wire w4; - wire [0:15] w5; - wire [0:23] w6; - wire [0:15] w7; - wire [0:23] w8; - wire [0:15] w9; - wire [0:7] w10; - wire [0:23] w11; - wire [0:7] w12; - wire [0:7] w13; - wire [0:7] w14; - wire [0:7] w15; - wire [0:7] w16; - wire [0:7] w17; + wire [15:0] w5; + wire [23:0] w6; + wire [15:0] w7; + wire [23:0] w8; + wire [15:0] w9; + wire [7:0] w10; + wire [23:0] w11; + wire [7:0] w12; + wire [7:0] w13; + wire [7:0] w14; + wire [7:0] w15; + wire [7:0] w16; + wire [7:0] w17; assign v4642b6 = w4; assign w6 = v7959e8; assign w8 = vb5a2f2; @@ -2769,9 +2784,9 @@ module vab13f0 ( output [15:0] vf0a06e, output [7:0] v5246f6 ); - wire [0:23] w0; - wire [0:15] w1; - wire [0:7] w2; + wire [23:0] w0; + wire [15:0] w1; + wire [7:0] w2; assign w0 = vb18564; assign vf0a06e = w1; assign v5246f6 = w2; @@ -2802,9 +2817,9 @@ module va52e3b ( input [15:0] vbf8961, output [23:0] v6d326e ); - wire [0:15] w0; - wire [0:23] w1; - wire [0:7] w2; + wire [15:0] w0; + wire [23:0] w1; + wire [7:0] w2; assign w0 = vbf8961; assign v6d326e = w1; assign w2 = vf7d213; @@ -2836,12 +2851,12 @@ module v857d2e ( input vccca56, output [7:0] v19a59f ); - wire [0:7] w0; - wire [0:7] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:3] w4; - wire [0:3] w5; + wire [7:0] w0; + wire [7:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [3:0] w4; + wire [3:0] w5; wire w6; wire w7; wire w8; @@ -2896,8 +2911,8 @@ module v370cd6 ( wire w3; wire w4; wire w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -3097,9 +3112,9 @@ module v9c1f69 ( output [2:0] v1045ee, output [4:0] v52d10b ); - wire [0:7] w0; - wire [0:4] w1; - wire [0:2] w2; + wire [7:0] w0; + wire [4:0] w1; + wire [2:0] w2; assign w0 = vcc8c7c; assign v52d10b = w1; assign v1045ee = w2; @@ -3134,8 +3149,8 @@ module v89d234 #( output [7:0] vb1c024 ); localparam p0 = v422d28; - wire [0:7] w1; - wire [0:7] w2; + wire [7:0] w1; + wire [7:0] w2; wire w3; wire w4; assign vb1c024 = w1; @@ -3168,11 +3183,13 @@ module v89d234_v9148cb #( ); localparam N = 8; - reg [N-1:0] q = INI; + reg [N-1:0] qi = INI; always @(posedge clk) if (load) - q <= d; + qi <= d; + + assign q = qi; endmodule //---- Top entity module vffc517 #( @@ -3181,7 +3198,7 @@ module vffc517 #( output [7:0] va0aeac ); localparam p0 = vc5c8ea; - wire [0:7] w1; + wire [7:0] w1; assign va0aeac = w1; vffc517_v465065 #( .VALUE(p0) @@ -3210,17 +3227,17 @@ module v1bbb5b ( input v2d3366, output [7:0] v9d2a6a ); - wire [0:3] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:3] w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [3:0] w4; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; - wire [0:3] w10; + wire [3:0] w10; assign v9d2a6a = w1; assign w2 = v2a1cbe; assign w3 = v9d7ae8; @@ -3271,10 +3288,10 @@ module v952eda ( wire w0; wire w1; wire w2; - wire [0:3] w3; + wire [3:0] w3; wire w4; - wire [0:3] w5; - wire [0:3] w6; + wire [3:0] w5; + wire [3:0] w6; wire w7; wire w8; wire w9; @@ -3358,8 +3375,8 @@ module v78be07 ( output v2ce16c, output [6:0] vdb77b6 ); - wire [0:7] w0; - wire [0:6] w1; + wire [7:0] w0; + wire [6:0] w1; wire w2; assign w0 = vcc8c7c; assign vdb77b6 = w1; @@ -3448,7 +3465,7 @@ module vda0861 #( output [7:0] vffb58f ); localparam p0 = vfffc23; - wire [0:7] w1; + wire [7:0] w1; assign vffb58f = w1; vffc517 #( .vc5c8ea(p0) diff --git a/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.gtkw b/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.gtkw index dbec1818..33b2a119 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.gtkw +++ b/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.gtkw @@ -1,21 +1,4 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Wed Nov 20 22:19:57 2024 -[*] -[dumpfile] "/Users/user/projects/apio_dev/repo/test-examples/TB/alhambra-ii/icestudio/ledon/_build/ledon_tb.vcd" -[dumpfile_mtime] "Wed Nov 20 22:19:35 2024" -[dumpfile_size] 580 -[savefile] "/Users/user/projects/apio_dev/repo/test-examples/TB/alhambra-ii/icestudio/ledon/ledon_tb.gtkw" -[timestart] 0 -[size] 1000 600 -[pos] -1 -1 -*-14.929331 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[sst_width] 253 -[signals_width] 78 -[sst_expanded] 1 -[sst_vpaned_height] 158 -@29 -[color] 1 +[*] Code generated by Icestudio 0.13.2w202501120101 +[*] Sun, 12 Jan 2025 00:12:49 GMT + main_tb.LED -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.v b/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.v index 3e42cbd1..e0e314c1 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.v +++ b/test-examples/ice40/alhambra-ii/icestudio-ledon/ledon_tb.v @@ -1,9 +1,15 @@ -// Code generated by Icestudio 0.9.2w202204260904 -// Thu, 28 Apr 2022 08:35:07 GMT +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules +// Sun, 12 Jan 2025 00:12:40 GMT // Testbench template `default_nettype none +`define DUMPSTR(x) `"x.vcd`" `timescale 10 ns / 1 ns @@ -22,7 +28,8 @@ module main_tb ); initial begin - // Dump vars to the output .vcd file + // File were to store the simulation results + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); $dumpvars(0, main_tb); // TODO: initialize the registers here diff --git a/test-examples/ice40/alhambra-ii/icestudio-ledon/main.pcf b/test-examples/ice40/alhambra-ii/icestudio-ledon/main.pcf index 1ea2233a..33483a8d 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-ledon/main.pcf +++ b/test-examples/ice40/alhambra-ii/icestudio-ledon/main.pcf @@ -1,4 +1,4 @@ -# Code generated by Icestudio 0.9.2w202204260904 +# Code generated by Icestudio 0.13.2w202501120101 set_io v8bfc7f 45 set_io vinit[0] 44 diff --git a/test-examples/ice40/alhambra-ii/icestudio-ledon/main.v b/test-examples/ice40/alhambra-ii/icestudio-ledon/main.v index 16a7b6eb..5b8b6694 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-ledon/main.v +++ b/test-examples/ice40/alhambra-ii/icestudio-ledon/main.v @@ -1,11 +1,16 @@ -// Code generated by Icestudio 0.9.2w202204260904 +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules `default_nettype none //---- Top entity module main ( output v8bfc7f, - output [0:6] vinit + output [6:0 ] vinit ); wire w0; assign v8bfc7f = w0; diff --git a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.gtkw b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.gtkw index 5bf6f269..58eb6b2b 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.gtkw +++ b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.gtkw @@ -1,5 +1,5 @@ -[*] Code generated by Icestudio 0.13.2w202501111101 -[*] Sat, 11 Jan 2025 22:36:32 GMT +[*] Code generated by Icestudio 0.13.2w202501120101 +[*] Sun, 12 Jan 2025 00:14:45 GMT main_tb.Button main_tb.Button diff --git a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.v b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.v index 8807546b..23fa7a82 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.v +++ b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/01-LEDs-buttons_tb.v @@ -1,9 +1,15 @@ -// Code generated by Icestudio 0.9.2w202204260904 -// Thu, 28 Apr 2022 10:12:59 GMT +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules +// Sun, 12 Jan 2025 00:14:33 GMT // Testbench template `default_nettype none +`define DUMPSTR(x) `"x.vcd`" `timescale 10 ns / 1 ns @@ -13,38 +19,44 @@ module main_tb // Simulation time: 100ns (10 * 10ns) parameter DURATION = 10; + // TODO: edit the module parameters here + // e.g. localparam constant_value = 1; + localparam constant_Constant = 4'hA; + localparam constant_Constant = 4'h5; + // Input/Output - reg Button1; - reg Button2; - wire LED7; - wire LED6; + reg Button; + reg Button; + wire LED; + wire LED; wire [3:0] LEDs; - wire LED5; - wire LED4; + wire LED; + wire LED; // Module instance - main MAIN ( - .v17b894(Button1), - .vf8383a(Button2), - .v7b511e(LED7), - .v6ef206(LED6), + main #( + .v2af3e8(constant_Constant), + .v98e11a(constant_Constant) + ) MAIN ( + .v17b894(Button), + .vf8383a(Button), + .v7b511e(LED), + .v6ef206(LED), .v1469d9(LEDs), - .v6898ff(LED5), - .v1e39f8(LED4) + .v6898ff(LED), + .v1e39f8(LED) ); initial begin - // Dump vars to the output .vcd file + // File were to store the simulation results + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); $dumpvars(0, main_tb); // TODO: initialize the registers here // e.g. value = 1; // e.g. #2 value = 0; - Button1 = 0; - Button2 = 0; - - #5 Button1 = 1; - Button2 = 1; + Button = 0; + Button = 0; #(DURATION) $display("End of simulation"); $finish; diff --git a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.pcf b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.pcf index f0dae182..411fd6c5 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.pcf +++ b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.pcf @@ -1,4 +1,4 @@ -# Code generated by Icestudio 0.13.2w202501111101 +# Code generated by Icestudio 0.13.2w202501120101 set_io v7b511e 37 set_io v17b894 34 diff --git a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.v b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.v index dc25e002..83ceb586 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.v +++ b/test-examples/ice40/alhambra-ii/icestudio-leds-buttons/main.v @@ -1,4 +1,9 @@ -// Code generated by Icestudio 0.13.2w202501111101 +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules `default_nettype none diff --git a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch.ice b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch.ice index 941bb4a4..7fd85be3 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch.ice +++ b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch.ice @@ -102,14 +102,27 @@ "format": 10 }, "position": { - "x": 920, - "y": 112 + "x": 840, + "y": 56 }, "size": { "width": 264, "height": 128 } }, + { + "id": "7da5a2ae-df78-4cd3-b0f6-ca4e1ecc7866", + "type": "basic.constant", + "data": { + "name": "LoadROM", + "value": "1", + "local": false + }, + "position": { + "x": 1144, + "y": 184 + } + }, { "id": "0af214eb-b035-424a-990b-6c5abf7fc06e", "type": "6809d2a5bbb6276fc06b9f532c913d9b9fdf6157", @@ -284,6 +297,16 @@ "port": "59095723-3090-4699-b192-76cc465ab5b1" }, "size": 8 + }, + { + "source": { + "block": "7da5a2ae-df78-4cd3-b0f6-ca4e1ecc7866", + "port": "constant-out" + }, + "target": { + "block": "0af214eb-b035-424a-990b-6c5abf7fc06e", + "port": "373e2da9-a042-42e7-80dc-eb5970bc5787" + } } ] } @@ -2576,6 +2599,19 @@ "height": 128 } }, + { + "id": "373e2da9-a042-42e7-80dc-eb5970bc5787", + "type": "basic.constant", + "data": { + "name": "LoadROM", + "value": "1", + "local": false + }, + "position": { + "x": 1672, + "y": 600 + } + }, { "id": "7b4dbf66-5445-4e07-8a85-d2a39503c588", "type": "f1cffe0819474c7b4c36893b94dfd3817e260223", @@ -3388,6 +3424,22 @@ "port": "8783fd57-b5ab-4d9f-9ac5-42695f31426f" }, "vertices": [] + }, + { + "source": { + "block": "373e2da9-a042-42e7-80dc-eb5970bc5787", + "port": "constant-out" + }, + "target": { + "block": "41705626-0707-409a-8299-5183fdae5498", + "port": "619ce266-7179-4c61-824d-a1280aa6118a" + }, + "vertices": [ + { + "x": 1672, + "y": 704 + } + ] } ] } @@ -5437,14 +5489,27 @@ "format": 10 }, "position": { - "x": 1192, - "y": -24 + "x": 1168, + "y": -80 }, "size": { "width": 128, "height": 96 } }, + { + "id": "619ce266-7179-4c61-824d-a1280aa6118a", + "type": "basic.constant", + "data": { + "name": "", + "value": "0", + "local": false + }, + "position": { + "x": 1360, + "y": -40 + } + }, { "id": "b770c97e-fbbb-4a98-9621-86b92dc9b352", "type": "d30ca9ee4f35f6cb76d5e5701447fc2b739bc640", @@ -5613,7 +5678,8 @@ }, "target": { "block": "244d243e-2efb-453b-a899-d664746bdc63", - "port": "8b0a8a99-fd6c-41b8-826a-52f35e572df2" + "port": "8b0a8a99-fd6c-41b8-826a-52f35e572df2", + "size": 32 }, "vertices": [], "size": 32 @@ -5621,7 +5687,8 @@ { "source": { "block": "ef1919e6-115c-4414-b8ae-4e23bd8761b6", - "port": "8f148bce-756b-4117-84c1-67526a839881" + "port": "8f148bce-756b-4117-84c1-67526a839881", + "size": 32 }, "target": { "block": "9c25b52c-7567-45da-86ae-5e3562e1b829", @@ -5649,7 +5716,8 @@ { "source": { "block": "a7510180-8076-417f-85df-c28637f785c4", - "port": "out" + "port": "out", + "size": 32 }, "target": { "block": "94c6ef30-66d0-4e91-9533-228c16567ea0", @@ -5664,7 +5732,8 @@ }, "target": { "block": "314ee589-5dc1-4846-bf48-26139fa23881", - "port": "in" + "port": "in", + "size": 32 }, "size": 32 }, @@ -5757,6 +5826,16 @@ "block": "ef1919e6-115c-4414-b8ae-4e23bd8761b6", "port": "d80bfd80-1f6d-46af-b5de-5cd121ebe630" } + }, + { + "source": { + "block": "619ce266-7179-4c61-824d-a1280aa6118a", + "port": "constant-out" + }, + "target": { + "block": "ef1919e6-115c-4414-b8ae-4e23bd8761b6", + "port": "4a62fe00-9706-4d42-bea6-ea6bc8f0ebfb" + } } ] } @@ -6018,24 +6097,31 @@ "format": 10 }, "position": { - "x": 464, - "y": 56 + "x": 336, + "y": 40 }, "size": { "width": 200, "height": 72 } }, + { + "id": "4a62fe00-9706-4d42-bea6-ea6bc8f0ebfb", + "type": "basic.constant", + "data": { + "name": "", + "value": "0", + "local": false + }, + "position": { + "x": 640, + "y": 48 + } + }, { "id": "f5619044-1e4b-4218-bfc2-44eced6cb16a", "type": "basic.code", "data": { - "code": "//-- Address with\nlocalparam ADDR_WIDTH = 10;\n//-- Data with\nlocalparam DATA_WIDTH = 32;\n\n//-- Size of the memory\nlocalparam SIZE = 1 << ADDR_WIDTH;\n\n//-- Memory itself\nreg [DATA_WIDTH-1:0] mem[0:SIZE-1];\n\n//-- The data_out is a registered output (not a wire)\nreg data_out;\n\n//-- Reading port: Synchronous\nalways @(posedge clk)\nbegin\n data_out <= mem[addr];\nend\n\n//-- Writing port: Synchronous\nalways @(posedge clk)\nbegin\n if (wr) mem[addr] <= data_in;\nend\n\n\n//-- Init the memory\ninitial begin\n \n if (ROMF)\n $readmemh(ROMF, mem, 0, SIZE-1);\n \nend\n", - "params": [ - { - "name": "ROMF" - } - ], "ports": { "in": [ { @@ -6062,7 +6148,16 @@ "size": 32 } ] - } + }, + "params": [ + { + "name": "ROMF" + }, + { + "name": "loadROMF" + } + ], + "code": "//-- Address with\nlocalparam ADDR_WIDTH = 10;\n//-- Data with\nlocalparam DATA_WIDTH = 32;\n\n//-- Size of the memory\nlocalparam SIZE = 1 << ADDR_WIDTH;\n\n//-- Memory itself\nreg [DATA_WIDTH-1:0] mem[0:SIZE-1];\n\n//-- The data_out is a registered output (not a wire)\nreg [31:0]data_out_v;\nassign data_out=data_out_v;\n//-- Reading port: Synchronous\nalways @(posedge clk)\nbegin\n data_out_v <= mem[addr];\nend\n\n//-- Writing port: Synchronous\nalways @(posedge clk)\nbegin\n if (wr) mem[addr] <= data_in;\nend\n\n\n//-- Init the memory\ninitial begin\n \n if (loadROMF)\n $readmemh(ROMF, mem, 0, SIZE-1);\n \nend\n" }, "position": { "x": 312, @@ -6137,6 +6232,16 @@ "port": "data_in" }, "size": 32 + }, + { + "source": { + "block": "4a62fe00-9706-4d42-bea6-ea6bc8f0ebfb", + "port": "constant-out" + }, + "target": { + "block": "f5619044-1e4b-4218-bfc2-44eced6cb16a", + "port": "loadROMF" + } } ] } @@ -12390,7 +12495,7 @@ "id": "16e78204-213e-4833-9096-89d735307ec2", "type": "basic.code", "data": { - "code": "assign o3 = i[32:24];\nassign o2 = i[23:16];\nassign o1 = i[15:8];\nassign o0 = i[7:0];", + "code": "assign o3 = i[31:24];\nassign o2 = i[23:16];\nassign o1 = i[15:8];\nassign o0 = i[7:0];", "params": [], "ports": { "in": [ @@ -14557,7 +14662,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "//-- Initial value\nreg q = INI;\n\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n q <= d;", + "code": "//-- Initial value\nreg qi = INI;\nassign qi = q;\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n qi <= d;", "params": [ { "name": "INI" @@ -26266,7 +26371,7 @@ "id": "2b245a71-2d80-466b-955f-e3d61839fe25", "type": "basic.code", "data": { - "code": "// 1-Pull up\n\n//-- Place the IO block, configured as \n//-- input with pull-up\nSB_IO\n #(\n .PIN_TYPE(6'b 1010_01),\n \n //-- The pull-up is activated or not\n //-- depeding on the ON parameter\n .PULLUP(ON)\n \n ) input_pin (\n\n //--- Input pin\n .PACKAGE_PIN(i),\n \n //-- Block output\n .D_IN_0(o),\n \n //-- Configured as input\n .OUTPUT_ENABLE(1'b0),\n \n //-- Not used\n .D_OUT_0(1'b0)\n );", + "code": "// 1-Pull up\nwire pin_i;\nassign pin_i = i;\n//-- Place the IO block, configured as \n//-- input with pull-up\nSB_IO\n #(\n .PIN_TYPE(6'b 1010_01),\n \n //-- The pull-up is activated or not\n //-- depeding on the ON parameter\n .PULLUP(ON)\n \n ) input_pin (\n\n //--- Input pin\n .PACKAGE_PIN(pin_i),\n \n //-- Block output\n .D_IN_0(o),\n \n //-- Configured as input\n .OUTPUT_ENABLE(1'b0),\n \n //-- Not used\n .D_OUT_0(1'b0)\n );", "params": [ { "name": "ON" @@ -26621,7 +26726,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "//-- Initial value\nreg q = INI;\n\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n q <= d;", + "code": "//-- Initial value\nreg qi = INI;\nassign qi = q;\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n qi <= d;", "params": [ { "name": "INI" @@ -27676,7 +27781,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "reg q = INI;\n\nalways @(posedge clk)\n if (load)\n q <= d;", + "code": "reg qi = INI;\nassign q=qi;\nalways @(posedge clk)\n if (load)\n qi <= d;", "params": [ { "name": "INI" @@ -27886,7 +27991,7 @@ "id": "e5d5eb54-41fb-40de-908c-b1fe9b2ec085", "type": "basic.code", "data": { - "code": "//-- Numero de bits del contador\nlocalparam N = 16; \n\n//-- En contadores de N bits:\n//-- M = 2 ** N\n\n//-- Internamente usamos un bit mas\n//-- (N+1) bits\nreg [N:0] qi = 0;\n\nalways @(posedge clk)\n if (rst | ov)\n qi <= 0;\n else\n if (cnt)\n qi <= qi + 1;\n \nassign q = qi;\n\n//-- Comprobar overflow\nassign ov = (qi == M);\n ", + "code": "//-- Numero de bits del contador\nlocalparam N = 16; \n\n//-- En contadores de N bits:\n//-- M = 2 ** N\n\n//-- Internamente usamos un bit mas\n//-- (N+1) bits\nreg [N:0] qi = 0;\n\nalways @(posedge clk)\n if (rst | ov)\n qi <= 0;\n else\n if (cnt)\n qi <= qi + 1;\n \nassign q = qi[15:0];\n\n//-- Comprobar overflow\nassign ov = (qi == M);\n ", "params": [ { "name": "M" @@ -28299,7 +28404,7 @@ "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b", "type": "basic.code", "data": { - "code": "reg q = INI;\nalways @(posedge clk)\n q <= d;", + "code": "reg qi = INI;\nassign q=qi;\nalways @(posedge clk)\n qi <= d;", "params": [ { "name": "INI" diff --git a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.gtkw b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.gtkw index c4eb57ad..2e951fba 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.gtkw +++ b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.gtkw @@ -1,32 +1,5 @@ -[*] -[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Thu Apr 28 10:51:01 2022 -[*] -[dumpfile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/alhambra-ii/03-riscv-stop-watch/03-riscv-stop-watch_tb.vcd" -[dumpfile_mtime] "Thu Apr 28 10:47:25 2022" -[dumpfile_size] 264544 -[savefile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/alhambra-ii/03-riscv-stop-watch/03-riscv-stop-watch_tb.gtkw" -[timestart] 0 -[size] 1920 1043 -[pos] 1771 -116 -*-14.977386 74800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] main_tb. -[treeopen] main_tb.MAIN. -[treeopen] main_tb.MAIN.v40be46. -[treeopen] main_tb.MAIN.v60d27e. -[treeopen] main_tb.MAIN.v60d27e.v16f275. -[treeopen] main_tb.MAIN.v60d27e.v29c9ed. -[treeopen] main_tb.MAIN.v60d27e.v3f3e01. -[sst_width] 233 -[signals_width] 205 -[sst_expanded] 1 -[sst_vpaned_height] 426 -@28 -main_tb.clk +[*] Code generated by Icestudio 0.13.2w202501120101 +[*] Sun, 12 Jan 2025 00:40:28 GMT + main_tb.btn[1:0] -@22 main_tb.LED[7:0] -@23 -main_tb.MAIN.v60d27e.v29c9ed.v5c832d[31:0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.v b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.v index 550674f7..3ae2acbe 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.v +++ b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/03-riscv-stop-watch_tb.v @@ -1,9 +1,15 @@ -// Code generated by Icestudio 0.9.2w202204260904 -// Thu, 28 Apr 2022 10:45:15 GMT +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules +// Sun, 12 Jan 2025 00:40:01 GMT // Testbench template `default_nettype none +`define DUMPSTR(x) `"x.vcd`" `timescale 10 ns / 1 ns @@ -11,25 +17,27 @@ module main_tb ; // Simulation time: 100ns (10 * 10ns) - parameter DURATION = 500; + parameter DURATION = 10; + + // TODO: edit the module parameters here + // e.g. localparam constant_value = 1; + localparam constant_LoadROM = 1; -//-- Clock signal -reg clk = 0; -always #0.5 clk = ~clk; - // Input/Output reg [1:0] btn; wire [7:0] LED; // Module instance - main MAIN ( - .vclk(clk), + main #( + .vf892fe(constant_LoadROM) + ) MAIN ( .v2b2ed6(btn), .v036815(LED) ); initial begin - // Dump vars to the output .vcd file + // File were to store the simulation results + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); $dumpvars(0, main_tb); // TODO: initialize the registers here diff --git a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.pcf b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.pcf index 902183ec..b662274d 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.pcf +++ b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.pcf @@ -1,4 +1,4 @@ -# Code generated by Icestudio 0.8.1w202112300112 +# Code generated by Icestudio 0.13.2w202501120101 set_io v036815[7] 37 set_io v036815[6] 38 diff --git a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.v b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.v index a9f87da9..0b2a31a7 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.v +++ b/test-examples/ice40/alhambra-ii/icestudio-riscv-stop-watch/main.v @@ -1,33 +1,41 @@ -// Code generated by Icestudio 0.8.1w202112300112 +// Code generated by Icestudio 0.13.2w202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules `default_nettype none //---- Top entity module main #( - parameter v771499 = "v771499.list" + parameter v771499 = "v771499.list", + parameter vf892fe = 1 ) ( input [1:0] v2b2ed6, input vclk, output [7:0] v036815 ); localparam p1 = v771499; - wire [0:7] w0; - wire [0:1] w2; - wire [0:1] w3; - wire [0:7] w4; - wire w5; + localparam p5 = vf892fe; + wire [7:0] w0; + wire [1:0] w2; + wire [1:0] w3; + wire [7:0] w4; wire w6; + wire w7; assign v036815 = w0; assign w3 = v2b2ed6; - assign w5 = vclk; assign w6 = vclk; - assign w6 = w5; + assign w7 = vclk; + assign w7 = w6; v6809d2 #( - .v9298ae(p1) + .v9298ae(p1), + .v3969ac(p5) ) v60d27e ( .vc4e0ba(w0), .v6d8c97(w4), - .v6dda25(w5) + .v6dda25(w6) ); v8efab2 v40be46 ( .v0c06c3(w2), @@ -36,99 +44,102 @@ module main #( v7caf1c v46ef23 ( .ved9bf3(w2), .vcc8287(w3), - .v25ab12(w6) + .v25ab12(w7) ); endmodule //---- Top entity module v6809d2 #( - parameter v9298ae = "v9298ae.list" + parameter v9298ae = "v9298ae.list", + parameter v3969ac = 1 ) ( input v6dda25, input [7:0] v6d8c97, output [7:0] vc4e0ba ); localparam p3 = v9298ae; + localparam p4 = v3969ac; wire w0; wire w1; wire w2; - wire w4; wire w5; wire w6; wire w7; - wire [0:7] w8; - wire [0:7] w9; - wire w10; - wire [0:31] w11; - wire [0:31] w12; - wire [0:31] w13; - wire [0:31] w14; - wire [0:31] w15; - wire [0:3] w16; - wire w17; + wire w8; + wire [7:0] w9; + wire [7:0] w10; + wire w11; + wire [31:0] w12; + wire [31:0] w13; + wire [31:0] w14; + wire [31:0] w15; + wire [31:0] w16; + wire [3:0] w17; wire w18; wire w19; - assign w4 = v6dda25; + wire w20; assign w5 = v6dda25; assign w6 = v6dda25; assign w7 = v6dda25; - assign vc4e0ba = w8; - assign w9 = v6d8c97; + assign w8 = v6dda25; + assign vc4e0ba = w9; + assign w10 = v6d8c97; assign w1 = w0; - assign w5 = w4; - assign w6 = w4; assign w6 = w5; - assign w7 = w4; assign w7 = w5; assign w7 = w6; - assign w12 = w11; + assign w8 = w5; + assign w8 = w6; + assign w8 = w7; + assign w13 = w12; vf1cffe v468719 ( .ve9ba68(w0), .v79476f(w1), - .v6dda25(w4), - .v27dec4(w10), - .v9231ba(w11), - .vfc9252(w13), - .va0e119(w14), - .ve17e80(w16) + .v6dda25(w5), + .v27dec4(w11), + .v9231ba(w12), + .vfc9252(w14), + .va0e119(w15), + .ve17e80(w17) ); vd30ca9 v16f275 ( .v9fb85f(w0) ); v893ac6 #( - .vba98fe(p3) + .vba98fe(p3), + .vefeb71(p4) ) vc59f55 ( - .v6dda25(w5), - .v5d7e06(w11), - .v9a5b8a(w15) + .v6dda25(w6), + .v5d7e06(w12), + .v9a5b8a(w16) ); ve4c3a8 v29c9ed ( - .v5c832d(w12), - .v4642b6(w17), - .vd02149(w18), - .vafdfa0(w19) + .v5c832d(w13), + .v4642b6(w18), + .vd02149(w19), + .vafdfa0(w20) ); vf68661 v66eb94 ( - .v6dda25(w7), - .vfeb41a(w8), - .vf837fe(w13), - .ve9e5a1(w16), - .ve146f6(w19) + .v6dda25(w8), + .vfeb41a(w9), + .vf837fe(w14), + .ve9e5a1(w17), + .ve146f6(w20) ); v145d1e v3f3e01 ( - .vc74a9c(w9), - .vb76294(w14), - .vb79ed5(w15), - .v6287a6(w17), - .v19f646(w18) + .vc74a9c(w10), + .vb76294(w15), + .vb79ed5(w16), + .v6287a6(w18), + .v19f646(w19) ); v04e061 vb15d38 ( .v4642b6(w2), - .vd6bebe(w6) + .vd6bebe(w7) ); v3676a0 vd1c5e9 ( .v0e28cb(w2), - .vcbab45(w10) + .vcbab45(w11) ); endmodule @@ -150,12 +161,12 @@ module vf1cffe ( output v8d2eee ); wire w0; - wire [0:31] w1; + wire [31:0] w1; wire w2; wire w3; - wire [0:31] w4; - wire [0:31] w5; - wire [0:3] w6; + wire [31:0] w4; + wire [31:0] w5; + wire [3:0] w6; wire w7; wire w8; assign w0 = v27dec4; @@ -586,25 +597,27 @@ module vd30ca9_vb2eccd ( endmodule //---- Top entity module v893ac6 #( - parameter vba98fe = "vba98fe.list" + parameter vba98fe = "vba98fe.list", + parameter vefeb71 = 0 ) ( input v6dda25, input [31:0] v5d7e06, output [31:0] v9a5b8a ); localparam p6 = vba98fe; + localparam p7 = vefeb71; wire w0; - wire [0:31] w1; + wire [31:0] w1; wire w2; - wire [0:31] w3; - wire [0:9] w4; - wire [0:31] w5; - wire w7; - wire [0:31] w8; - wire [0:31] w9; - assign w7 = v6dda25; - assign v9a5b8a = w8; - assign w9 = v5d7e06; + wire [31:0] w3; + wire [9:0] w4; + wire [31:0] w5; + wire w8; + wire [31:0] w9; + wire [31:0] w10; + assign w8 = v6dda25; + assign v9a5b8a = w9; + assign w10 = v5d7e06; vd30ca9 vc98086 ( .v9fb85f(w0) ); @@ -615,13 +628,14 @@ module v893ac6 #( .v7c9bd8(w3) ); v675d07 #( - .v5a4ee6(p6) + .v5a4ee6(p6), + .v844270(p7) ) vdbacf7 ( .v23dc54(w2), .v6f4b70(w3), .vb261ad(w4), - .v922e3d(w7), - .vddff9f(w8) + .v922e3d(w8), + .vddff9f(w9) ); v794b6d va8ea8d ( .vef1612(w4), @@ -630,7 +644,7 @@ module v893ac6 #( vaaf5c4 ve8e400 ( .v712289(w0), .v51eedb(w1), - .v4f6beb(w9) + .v4f6beb(w10) ); vaaf5c4 v677471 ( .v4f6beb(w1), @@ -650,7 +664,7 @@ module v2c97f6 #( output [31:0] v7c9bd8 ); localparam p0 = vfffc23; - wire [0:31] w1; + wire [31:0] w1; assign v7c9bd8 = w1; v959751 #( .vc5c8ea(p0) @@ -671,7 +685,7 @@ module v959751 #( output [31:0] vbc97e4 ); localparam p0 = vc5c8ea; - wire [0:31] w1; + wire [31:0] w1; assign vbc97e4 = w1; v959751_v465065 #( .VALUE(p0) @@ -695,7 +709,8 @@ module v959751_v465065 #( endmodule //---- Top entity module v675d07 #( - parameter v5a4ee6 = "v5a4ee6.list" + parameter v5a4ee6 = "v5a4ee6.list", + parameter v844270 = 0 ) ( input v922e3d, input [9:0] vb261ad, @@ -704,18 +719,20 @@ module v675d07 #( output [31:0] vddff9f ); localparam p2 = v5a4ee6; + localparam p6 = v844270; wire w0; wire w1; - wire [0:9] w3; - wire [0:31] w4; - wire [0:31] w5; + wire [9:0] w3; + wire [31:0] w4; + wire [31:0] w5; assign w0 = v922e3d; assign w1 = v23dc54; assign w3 = vb261ad; assign vddff9f = w4; assign w5 = v6f4b70; v675d07_vbaa912 #( - .ROMF(p2) + .ROMF(p2), + .loadROMF(p6) ) vbaa912 ( .clk(w0), .wr(w1), @@ -732,7 +749,8 @@ endmodule //--------------------------------------------------- module v675d07_vbaa912 #( - parameter ROMF = 0 + parameter ROMF = 0, + parameter loadROMF = 0 ) ( input clk, input [9:0] addr, @@ -752,12 +770,12 @@ module v675d07_vbaa912 #( reg [DATA_WIDTH-1:0] mem[0:SIZE-1]; //-- The data_out is a registered output (not a wire) - reg data_out; - + reg [31:0]data_out_v; + assign data_out=data_out_v; //-- Reading port: Synchronous always @(posedge clk) begin - data_out <= mem[addr]; + data_out_v <= mem[addr]; end //-- Writing port: Synchronous @@ -770,7 +788,7 @@ module v675d07_vbaa912 #( //-- Init the memory initial begin - if (ROMF) + if (loadROMF) $readmemh(ROMF, mem, 0, SIZE-1); end @@ -782,9 +800,9 @@ module v794b6d ( output [21:0] v51fb1f, output [9:0] vef1612 ); - wire [0:31] w0; - wire [0:9] w1; - wire [0:21] w2; + wire [31:0] w0; + wire [9:0] w1; + wire [21:0] w2; assign w0 = ve841af; assign vef1612 = w1; assign v51fb1f = w2; @@ -816,11 +834,11 @@ module vaaf5c4 ( output [31:0] v51eedb, output v7e4f0f ); - wire [0:31] w0; + wire [31:0] w0; wire w1; wire w2; - wire [0:30] w3; - wire [0:31] w4; + wire [30:0] w3; + wire [31:0] w4; assign w0 = v4f6beb; assign v7e4f0f = w1; assign w2 = v712289; @@ -848,9 +866,9 @@ module vecd30a ( output [30:0] v11ef80, output v8d1a42 ); - wire [0:31] w0; + wire [31:0] w0; wire w1; - wire [0:30] w2; + wire [30:0] w2; assign w0 = ve841af; assign v8d1a42 = w1; assign v11ef80 = w2; @@ -881,8 +899,8 @@ module v51b3c0 ( input [30:0] vd40455, output [31:0] v7d0a31 ); - wire [0:31] w0; - wire [0:30] w1; + wire [31:0] w0; + wire [30:0] w1; wire w2; assign v7d0a31 = w0; assign w1 = vd40455; @@ -921,14 +939,14 @@ module ve4c3a8 #( wire w0; wire w1; wire w2; - wire [0:14] w3; - wire [0:4] w4; - wire [0:4] w5; - wire [0:4] w6; - wire [0:4] w7; - wire [0:2] w9; - wire [0:31] w10; - wire [0:31] w11; + wire [14:0] w3; + wire [4:0] w4; + wire [4:0] w5; + wire [4:0] w6; + wire [4:0] w7; + wire [2:0] w9; + wire [31:0] w10; + wire [31:0] w11; wire w12; wire w13; wire w14; @@ -1073,7 +1091,7 @@ module v9a2795 ( ); wire w0; wire w1; - wire [0:2] w2; + wire [2:0] w2; wire w3; assign v3f8943 = w0; assign v64d863 = w1; @@ -1109,9 +1127,9 @@ module va7b832 ( output [16:0] v62a8c1, output [14:0] v29a212 ); - wire [0:31] w0; - wire [0:14] w1; - wire [0:16] w2; + wire [31:0] w0; + wire [14:0] w1; + wire [16:0] w2; assign w0 = ve841af; assign v29a212 = w1; assign v62a8c1 = w2; @@ -1142,9 +1160,9 @@ module vef0f91 ( output [4:0] vfa86aa, output [9:0] vbdb2c8 ); - wire [0:14] w0; - wire [0:9] w1; - wire [0:4] w2; + wire [14:0] w0; + wire [9:0] w1; + wire [4:0] w2; assign w0 = vcbe66f; assign vbdb2c8 = w1; assign vfa86aa = w2; @@ -1176,14 +1194,14 @@ module v1cc648 ( output v4642b6 ); wire w0; - wire [0:4] w1; - wire [0:4] w2; + wire [4:0] w1; + wire [4:0] w2; wire w3; wire w4; wire w5; - wire [0:3] w6; + wire [3:0] w6; wire w7; - wire [0:3] w8; + wire [3:0] w8; assign v4642b6 = w0; assign w1 = vfad888; assign w2 = vd80e4f; @@ -1290,8 +1308,8 @@ module v91f34c ( output v53baa6, output [3:0] v479af4 ); - wire [0:3] w0; - wire [0:4] w1; + wire [3:0] w0; + wire [4:0] w1; wire w2; assign v479af4 = w0; assign w1 = v427dd1; @@ -1325,8 +1343,8 @@ module v438230 ( output v4642b6 ); wire w0; - wire [0:3] w1; - wire [0:3] w2; + wire [3:0] w1; + wire [3:0] w2; wire w3; wire w4; wire w5; @@ -1402,7 +1420,7 @@ module vc4f23a ( wire w1; wire w2; wire w3; - wire [0:3] w4; + wire [3:0] w4; assign v3f8943 = w0; assign v64d863 = w1; assign vda577d = w2; @@ -1484,7 +1502,7 @@ module v108a6d #( output [4:0] v6ece80 ); localparam p0 = vfffc23; - wire [0:4] w1; + wire [4:0] w1; assign v6ece80 = w1; v3693fc #( .vc5c8ea(p0) @@ -1505,7 +1523,7 @@ module v3693fc #( output [4:0] vc8d3b9 ); localparam p0 = vc5c8ea; - wire [0:4] w1; + wire [4:0] w1; assign vc8d3b9 = w1; v3693fc_v465065 #( .VALUE(p0) @@ -1533,9 +1551,9 @@ module ve500df ( output [28:0] vfc82fb, output [2:0] vbb2522 ); - wire [0:31] w0; - wire [0:2] w1; - wire [0:28] w2; + wire [31:0] w0; + wire [2:0] w1; + wire [28:0] w2; assign w0 = ve841af; assign vbb2522 = w1; assign vfc82fb = w2; @@ -1569,12 +1587,12 @@ module vf68661 ( output [7:0] vfeb41a ); wire w0; - wire [0:7] w1; + wire [7:0] w1; wire w2; - wire [0:7] w3; + wire [7:0] w3; wire w4; - wire [0:31] w5; - wire [0:3] w6; + wire [31:0] w5; + wire [3:0] w6; wire w7; assign vfeb41a = w3; assign w4 = v6dda25; @@ -1613,7 +1631,7 @@ module vf61fa3 ( output vcbab45 ); wire w0; - wire [0:3] w1; + wire [3:0] w1; wire w2; wire w3; wire w4; @@ -1728,11 +1746,11 @@ module v468a05 ( output [7:0] vf93ecb, output [7:0] vc6471a ); - wire [0:31] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:7] w4; + wire [31:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [7:0] w4; assign w0 = ve841af; assign vc6471a = w1; assign vf93ecb = w2; @@ -1760,7 +1778,7 @@ module v468a05_v9a2a06 ( output [7:0] o1, output [7:0] o0 ); - assign o3 = i[32:24]; + assign o3 = i[31:24]; assign o2 = i[23:16]; assign o1 = i[15:8]; assign o0 = i[7:0]; @@ -1772,12 +1790,12 @@ module v857d2e ( input vccca56, output [7:0] v19a59f ); - wire [0:7] w0; - wire [0:7] w1; - wire [0:3] w2; - wire [0:3] w3; - wire [0:3] w4; - wire [0:3] w5; + wire [7:0] w0; + wire [7:0] w1; + wire [3:0] w2; + wire [3:0] w3; + wire [3:0] w4; + wire [3:0] w5; wire w6; wire w7; wire w8; @@ -1825,9 +1843,9 @@ module v6bdcd9 ( output [3:0] v651522, output [3:0] v2cc41f ); - wire [0:3] w0; - wire [0:3] w1; - wire [0:7] w2; + wire [3:0] w0; + wire [3:0] w1; + wire [7:0] w2; assign v651522 = w0; assign v2cc41f = w1; assign w2 = vcc8c7c; @@ -1858,9 +1876,9 @@ module vafb28f ( input [3:0] v3c88fc, output [7:0] va9ac17 ); - wire [0:7] w0; - wire [0:3] w1; - wire [0:3] w2; + wire [7:0] w0; + wire [3:0] w1; + wire [3:0] w2; assign va9ac17 = w0; assign w1 = v515fe7; assign w2 = v3c88fc; @@ -1898,8 +1916,8 @@ module v370cd6 ( wire w3; wire w4; wire w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -2131,13 +2149,13 @@ module v053dc2_vb8adf8 #( output q ); //-- Initial value - reg q = INI; - + reg qi = INI; + assign qi = q; //-- Capture the input data //-- on the rising edge of //-- the system clock always @(posedge clk) - q <= d; + qi <= d; endmodule //---- Top entity module v84f0a1 ( @@ -2151,7 +2169,7 @@ module v84f0a1 ( wire w1; wire w2; wire w3; - wire [0:3] w4; + wire [3:0] w4; assign w0 = vee8a83; assign w1 = v03aaf0; assign w2 = vf8041d; @@ -2190,15 +2208,15 @@ module v145d1e ( input v19f646, output [31:0] vb76294 ); - wire [0:31] w0; - wire [0:31] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:7] w4; - wire [0:31] w5; - wire [0:31] w6; - wire [0:31] w7; - wire [0:7] w8; + wire [31:0] w0; + wire [31:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [7:0] w4; + wire [31:0] w5; + wire [31:0] w6; + wire [31:0] w7; + wire [7:0] w8; wire w9; wire w10; assign w6 = vb79ed5; @@ -2248,25 +2266,25 @@ module v15006c ( input v2d3366, output [31:0] vd99bd0 ); - wire [0:7] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:31] w3; - wire [0:31] w4; - wire [0:31] w5; - wire [0:7] w6; - wire [0:7] w7; - wire [0:7] w8; + wire [7:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [31:0] w3; + wire [31:0] w4; + wire [31:0] w5; + wire [7:0] w6; + wire [7:0] w7; + wire [7:0] w8; wire w9; wire w10; wire w11; wire w12; - wire [0:7] w13; - wire [0:7] w14; - wire [0:7] w15; - wire [0:7] w16; - wire [0:7] w17; - wire [0:7] w18; + wire [7:0] w13; + wire [7:0] w14; + wire [7:0] w15; + wire [7:0] w16; + wire [7:0] w17; + wire [7:0] w18; assign vd99bd0 = w3; assign w4 = v3d79e8; assign w5 = v53354a; @@ -2339,17 +2357,17 @@ module v1bbb5b ( input v2d3366, output [7:0] v9d2a6a ); - wire [0:3] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:3] w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [3:0] w4; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; - wire [0:3] w10; + wire [3:0] w10; assign v9d2a6a = w1; assign w2 = v2a1cbe; assign w3 = v9d7ae8; @@ -2400,10 +2418,10 @@ module v952eda ( wire w0; wire w1; wire w2; - wire [0:3] w3; + wire [3:0] w3; wire w4; - wire [0:3] w5; - wire [0:3] w6; + wire [3:0] w5; + wire [3:0] w6; wire w7; wire w8; wire w9; @@ -2489,11 +2507,11 @@ module v78e0a3 ( input [7:0] v29bdec, output [31:0] v7d0a31 ); - wire [0:31] w0; - wire [0:7] w1; - wire [0:7] w2; - wire [0:7] w3; - wire [0:7] w4; + wire [31:0] w0; + wire [7:0] w1; + wire [7:0] w2; + wire [7:0] w3; + wire [7:0] w4; assign v7d0a31 = w0; assign w1 = v29bdec; assign w2 = vea9d11; @@ -2531,7 +2549,7 @@ module vda0861 #( output [7:0] vffb58f ); localparam p0 = vfffc23; - wire [0:7] w1; + wire [7:0] w1; assign vffb58f = w1; vffc517 #( .vc5c8ea(p0) @@ -2552,7 +2570,7 @@ module vffc517 #( output [7:0] va0aeac ); localparam p0 = vc5c8ea; - wire [0:7] w1; + wire [7:0] w1; assign va0aeac = w1; vffc517_v465065 #( .VALUE(p0) @@ -2591,11 +2609,11 @@ module v04e061 #( wire w5; wire w6; wire w7; - wire [0:4] w8; + wire [4:0] w8; wire w9; wire w10; wire w11; - wire [0:4] w12; + wire [4:0] w12; assign v4642b6 = w2; assign vd9f5b6 = w6; assign vb385cd = w8; @@ -2732,10 +2750,10 @@ module vaf1249 ( output ve37344 ); wire w0; - wire [0:4] w1; - wire [0:4] w2; + wire [4:0] w1; + wire [4:0] w2; wire w3; - wire [0:4] w4; + wire [4:0] w4; wire w5; assign w0 = ve556f1; assign w3 = v6dda25; @@ -2767,12 +2785,12 @@ module v6ed669 ( input [4:0] v35dd11, output [4:0] vcc30ea ); - wire [0:4] w0; - wire [0:3] w1; + wire [4:0] w0; + wire [3:0] w1; wire w2; - wire [0:3] w3; + wire [3:0] w3; wire w4; - wire [0:4] w5; + wire [4:0] w5; wire w6; wire w7; wire w8; @@ -2870,8 +2888,8 @@ module v5c75f6 ( wire w3; wire w4; wire w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -2955,9 +2973,9 @@ module vcdce79 ( input [3:0] v167ed7, output [4:0] v6a2e9e ); - wire [0:4] w0; + wire [4:0] w0; wire w1; - wire [0:3] w2; + wire [3:0] w2; assign v6a2e9e = w0; assign w1 = vee8a83; assign w2 = v167ed7; @@ -2992,8 +3010,8 @@ module vd0bb30 #( ); localparam p1 = v6c5139; wire w0; - wire [0:4] w2; - wire [0:4] w3; + wire [4:0] w2; + wire [4:0] w3; assign v4642b6 = w0; assign w2 = vd03823; assign vb4c454 = w3; @@ -3021,9 +3039,9 @@ module va17f79 #( ); localparam p1 = vd73390; wire w0; - wire [0:4] w2; - wire [0:4] w3; - wire [0:4] w4; + wire [4:0] w2; + wire [4:0] w3; + wire [4:0] w4; assign v4642b6 = w0; assign w3 = va6f14e; assign v919f01 = w4; @@ -3054,15 +3072,15 @@ module v0cfc7a ( ); wire w0; wire w1; - wire [0:4] w2; - wire [0:4] w3; - wire [0:4] w4; + wire [4:0] w2; + wire [4:0] w3; + wire [4:0] w4; wire w5; - wire [0:3] w6; + wire [3:0] w6; wire w7; - wire [0:3] w8; + wire [3:0] w8; wire w9; - wire [0:3] w10; + wire [3:0] w10; assign w2 = vbb6b94; assign w3 = v225d34; assign vae8b91 = w4; @@ -3178,9 +3196,9 @@ module v25966b ( wire w2; wire w3; wire w4; - wire [0:3] w5; - wire [0:3] w6; - wire [0:3] w7; + wire [3:0] w5; + wire [3:0] w6; + wire [3:0] w7; wire w8; wire w9; wire w10; @@ -3298,9 +3316,9 @@ module v51353d ( wire w5; wire w6; wire w7; - wire [0:4] w8; + wire [4:0] w8; wire w9; - wire [0:4] w10; + wire [4:0] w10; wire w11; wire w12; wire w13; @@ -3386,7 +3404,7 @@ module v60f5a9 ( wire w2; wire w3; wire w4; - wire [0:4] w5; + wire [4:0] w5; assign v3f8943 = w0; assign v64d863 = w1; assign vda577d = w2; @@ -3434,7 +3452,7 @@ module v36cddd ( ); wire w0; wire w1; - wire [0:4] w2; + wire [4:0] w2; wire w3; wire w4; wire w5; @@ -3476,9 +3494,9 @@ module v8efab2 ( input [1:0] v0c06c3, output [7:0] v20cbde ); - wire [0:7] w0; - wire [0:1] w1; - wire [0:5] w2; + wire [7:0] w0; + wire [1:0] w1; + wire [5:0] w2; assign v20cbde = w0; assign w1 = v0c06c3; v2ae6c6 vab1711 ( @@ -3502,9 +3520,9 @@ module v2ae6c6 ( input [1:0] v05ee31, output [7:0] va9ac17 ); - wire [0:7] w0; - wire [0:1] w1; - wire [0:5] w2; + wire [7:0] w0; + wire [1:0] w1; + wire [5:0] w2; assign va9ac17 = w0; assign w1 = v05ee31; assign w2 = v164ff1; @@ -3536,7 +3554,7 @@ module v54ad57 #( output [5:0] ve45beb ); localparam p0 = vfffc23; - wire [0:5] w1; + wire [5:0] w1; assign ve45beb = w1; va5ad63 #( .vc5c8ea(p0) @@ -3557,7 +3575,7 @@ module va5ad63 #( output [5:0] vbbba94 ); localparam p0 = vc5c8ea; - wire [0:5] w1; + wire [5:0] w1; assign vbbba94 = w1; va5ad63_v465065 #( .VALUE(p0) @@ -3592,8 +3610,8 @@ module v7caf1c #( localparam p7 = v803182; localparam p8 = v803182; localparam p9 = v17ea21; - wire [0:1] w0; - wire [0:1] w1; + wire [1:0] w0; + wire [1:0] w1; wire w2; wire w3; wire w4; @@ -3646,7 +3664,7 @@ module vfc9dac ( ); wire w0; wire w1; - wire [0:1] w2; + wire [1:0] w2; assign v3f8943 = w0; assign v64d863 = w1; assign w2 = v8b19dd; @@ -3679,7 +3697,7 @@ module vd4bd04 ( ); wire w0; wire w1; - wire [0:1] w2; + wire [1:0] w2; assign w0 = vee8a83; assign w1 = v03aaf0; assign v67a3fc = w2; @@ -3789,7 +3807,8 @@ module v6c3aff_v34955f #( output o ); // 1-Pull up - + wire pin_i; + assign pin_i = i; //-- Place the IO block, configured as //-- input with pull-up SB_IO @@ -3803,7 +3822,7 @@ module v6c3aff_v34955f #( ) input_pin ( //--- Input pin - .PACKAGE_PIN(i), + .PACKAGE_PIN(pin_i), //-- Block output .D_IN_0(o), @@ -3886,13 +3905,13 @@ module vc8cfba_vb8adf8 #( output q ); //-- Initial value - reg q = INI; - + reg qi = INI; + assign qi = q; //-- Capture the input data //-- on the rising edge of //-- the system clock always @(posedge clk) - q <= d; + qi <= d; endmodule //---- Top entity module v5645be #( @@ -4086,11 +4105,11 @@ module v93adf6_vb8adf8 #( input load, output q ); - reg q = INI; - + reg qi = INI; + assign q=qi; always @(posedge clk) if (load) - q <= d; + qi <= d; endmodule //---- Top entity module v8d4ef5 #( @@ -4107,7 +4126,7 @@ module v8d4ef5 #( wire w2; wire w3; wire w4; - wire [0:15] w5; + wire [15:0] w5; assign w0 = ve61673; assign w2 = v7c533e; assign w3 = vdd729a; @@ -4156,7 +4175,7 @@ module v8d4ef5_vbd6086 #( if (cnt) qi <= qi + 1; - assign q = qi; + assign q = qi[15:0]; //-- Comprobar overflow assign ov = (qi == M); @@ -4232,7 +4251,8 @@ module v1c7dae_vb8adf8 #( input d, output q ); - reg q = INI; + reg qi = INI; + assign q=qi; always @(posedge clk) - q <= d; + qi <= d; endmodule diff --git a/test-examples/ice40/alhambra-ii/icestudio-tff/main.pcf b/test-examples/ice40/alhambra-ii/icestudio-tff/main.pcf index 30f1d892..56bd9908 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-tff/main.pcf +++ b/test-examples/ice40/alhambra-ii/icestudio-tff/main.pcf @@ -1,7 +1,6 @@ -# Code generated by Icestudio 0.9.2w202204260904 +# Code generated by Icestudio 0.13.2w202501120101202501120101 set_io v8bfc7f 45 -set_io vclk 49 set_io vinit[0] 44 set_io vinit[1] 43 set_io vinit[2] 42 diff --git a/test-examples/ice40/alhambra-ii/icestudio-tff/main.v b/test-examples/ice40/alhambra-ii/icestudio-tff/main.v index 87866a53..78c0793d 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-tff/main.v +++ b/test-examples/ice40/alhambra-ii/icestudio-tff/main.v @@ -1,130 +1,47 @@ -// Code generated by Icestudio 0.9.2w202204260904 +// Code generated by Icestudio 0.13.2w202501120101202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules `default_nettype none //---- Top entity module main ( - input vclk, output v8bfc7f, - output [0:6] vinit + output [6:0 ] vinit ); wire w0; - wire w1; assign v8bfc7f = w0; - assign w1 = vclk; - v786767 vbc37d2 ( - .v4642b6(w0), - .v6dda25(w1) + vfebcfe vb9eb2f ( + .v9fb85f(w0) ); assign vinit = 7'b0000000; endmodule //---- Top entity -module v786767 #( - parameter v8bcde4 = 0 -) ( - input v6dda25, - output v4642b6 +module vfebcfe ( + output v9fb85f ); - localparam p3 = v8bcde4; wire w0; - wire w1; - wire w2; - wire w4; - assign v4642b6 = w2; - assign w4 = v6dda25; - assign w2 = w1; - v3676a0 v14ac37 ( - .vcbab45(w0), - .v0e28cb(w1) - ); - v053dc2 #( - .v71e305(p3) - ) vb6ab02 ( - .vf54559(w0), - .ve8318d(w1), - .va4102a(w4) - ); -endmodule - -//--------------------------------------------------- -//-- TFF -//-- - - - - - - - - - - - - - - - - - - - - - - - -- -//-- System TFF: It toogles its output on every system cycle -//--------------------------------------------------- -//---- Top entity -module v3676a0 ( - input v0e28cb, - output vcbab45 -); - wire w0; - wire w1; - assign w0 = v0e28cb; - assign vcbab45 = w1; - v3676a0_vd54ca1 vd54ca1 ( - .a(w0), - .q(w1) + assign v9fb85f = w0; + vfebcfe_vb2eccd vb2eccd ( + .q(w0) ); endmodule //--------------------------------------------------- -//-- NOT +//-- bit-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- -//-- NOT gate (Verilog implementation) +//-- Constant bit 1 //--------------------------------------------------- -module v3676a0_vd54ca1 ( - input a, +module vfebcfe_vb2eccd ( output q ); - //-- NOT Gate - assign q = ~a; - + //-- Constant bit-1 + assign q = 1'b1; -endmodule -//---- Top entity -module v053dc2 #( - parameter v71e305 = 0 -) ( - input va4102a, - input vf54559, - output ve8318d -); - localparam p2 = v71e305; - wire w0; - wire w1; - wire w3; - assign w0 = va4102a; - assign ve8318d = w1; - assign w3 = vf54559; - v053dc2_vb8adf8 #( - .INI(p2) - ) vb8adf8 ( - .clk(w0), - .q(w1), - .d(w3) - ); -endmodule - -//--------------------------------------------------- -//-- DFF -//-- - - - - - - - - - - - - - - - - - - - - - - - -- -//-- D Flip-flop (verilog implementation) -//--------------------------------------------------- - -module v053dc2_vb8adf8 #( - parameter INI = 0 -) ( - input clk, - input d, - output q -); - //-- Initial value - reg q = INI; - //-- Capture the input data - //-- on the rising edge of - //-- the system clock - always @(posedge clk) - q <= d; endmodule diff --git a/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.gtkw b/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.gtkw index acbbda0c..f3173920 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.gtkw +++ b/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.gtkw @@ -1,25 +1,4 @@ -[*] -[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Thu Apr 28 09:24:55 2022 -[*] -[dumpfile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/TB/alhambra-ii/icestudio/tff/tff_tb.vcd" -[dumpfile_mtime] "Thu Apr 28 09:24:05 2022" -[dumpfile_size] 1734 -[savefile] "/home/obijuan/Develop/FPGAwars/apio/test-examples/TB/alhambra-ii/icestudio/tff/tff_tb.gtkw" -[timestart] 0 -[size] 1860 1016 -[pos] -89 -89 -*-7.079701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] main_tb. -[sst_width] 233 -[signals_width] 94 -[sst_expanded] 1 -[sst_vpaned_height] 289 -@29 -main_tb.clk -@200 -- -@28 -main_tb.LED_test -[pattern_trace] 1 -[pattern_trace] 0 +[*] Code generated by Icestudio 0.13.2w202501120101202501120101 +[*] Sun, 12 Jan 2025 00:41:29 GMT + +main_tb.LED diff --git a/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.v b/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.v index 7eec303f..5d176e55 100644 --- a/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.v +++ b/test-examples/ice40/alhambra-ii/icestudio-tff/tff_tb.v @@ -1,33 +1,35 @@ -// Code generated by Icestudio 0.9.2w202204260904 -// Thu, 28 Apr 2022 08:42:19 GMT +// Code generated by Icestudio 0.13.2w202501120101202501120101 +// #START Verilator Linter rules: +/* verilator lint_off PINMISSING */ +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off WIDTHEXPAND */ +// #END Verilator Linter rules +// Sun, 12 Jan 2025 00:41:18 GMT // Testbench template `default_nettype none -`timescale 10 ps / 1 ps +`define DUMPSTR(x) `"x.vcd`" +`timescale 10 ns / 1 ns module main_tb ; // Simulation time: 100ns (10 * 10ns) - parameter DURATION = 50; + parameter DURATION = 10; -//-- Clock signal -reg clk = 0; -always #4.2 clk = ~clk; - // Input/Output - wire LED_test; + wire LED; // Module instance main MAIN ( - .vclk(clk), - .v8bfc7f(LED_test) + .v8bfc7f(LED) ); initial begin - // Dump vars to the output .vcd file + // File were to store the simulation results + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); $dumpvars(0, main_tb); // TODO: initialize the registers here