Atomic gemm for TP-AR and TP-RS overlap with P2P exchanges #732
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Signed-off-by: Sangkug Lym <slym@nvidia.com>
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@timmoon10 |
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/te-ci pytorch |
timmoon10
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Mar 26, 2024
Signed-off-by: Sangkug Lym <slym@nvidia.com>
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Fixed lint errors and reflected comments. |
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@timmoon10 Can we merge this PR? |
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/te-ci pytorch |
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/te-ci pytorch |
pggPL
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May 15, 2024
* Atomic gemm for TP-AR and TP-RS overlap with P2P exchanges Signed-off-by: Sangkug Lym <slym@nvidia.com> * FP8 reduction for atomic TP-RS with p2p exchange Signed-off-by: Sangkug Lym <slym@nvidia.com> * Fix Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> --------- Signed-off-by: Sangkug Lym <slym@nvidia.com> Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> Co-authored-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
pggPL
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May 23, 2024
* Atomic gemm for TP-AR and TP-RS overlap with P2P exchanges Signed-off-by: Sangkug Lym <slym@nvidia.com> * FP8 reduction for atomic TP-RS with p2p exchange Signed-off-by: Sangkug Lym <slym@nvidia.com> * Fix Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> --------- Signed-off-by: Sangkug Lym <slym@nvidia.com> Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> Co-authored-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com> Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
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atomic GEMMandring_exhcnagefor functionality.NVTE_AG_P2P_MULTI_ATOMIC=1uses a single kernel for TP-AG.num_splitsto 4 from 0, which is only valid for TP-RS overlap withpipelineoverlap.