microcode.cson

signals: [
  {
    name: 'aluYNWE'
    noOp: 1
  }
  {
    name: 'aluNOE'
    noOp: 1
  }
  {
    name: 'reg0NWE'
    noOp: 1
  }
  {
    name: 'reg1NWE'
    noOp: 1
  }
  {
    name: 'regAluSel'
    noOp: 0
  }
  {
    name: 'reg0BusNOE'
    noOp: 1
  }
  {
    name: 'reg1BusNOE'
    noOp: 1
  }
  {
    name: 'memPCLoadN'
    noOp: 1
  }
  {
    name: 'memSPUp'
    noOp: 0
  }
  {
    name: 'memSPNEn'
    noOp: 1
  }
  {
    name: 'memInstrNWE'
    noOp: 1
  }
  {
    name: 'memInstrNOE'
    noOp: 1
  }
  {
    name: 'memMar0NWE'
    noOp: 1
  }
  {
    name: 'memMar1NWE'
    noOp: 1
  }
  {
    name: 'memInstrImmToRamAddr' # not mar
    noOp: 1
  }
  {
    name: 'memRamNWE'
    noOp: 1
  }
  {
    name: 'memRamNOE'
    noOp: 1
  }
  {
    name: 'memPCNEn'
    noOp: 1
  }
  {
    name: 'memPCFromImm'
    noOp: 1
  }
  {
    name: 'memPCToRamN'
    noOp: 1
  }
  {
    name: 'instrFinishedN' # automatically in script
    noOp: 1
  }
  {
    name: 'busFFNOE'
    noOp: 1
  }
]
instructionFetch: [
  {
    memInstrNWE: 0
  }
  { # wait
    memPCNEn: 0
    memPCLoadN: 1
  }
]
instructions: [
  # alu
  {
    op: '000rsalu' # r = r x s (alu)
    cycles: [
      { # r x s into alu
        aluYNWE: 0
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
        regAluSel: 'r'
      }
      { # alu into r
        aluNOE: 0
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
    ]
  }
  {
    op: '001rsalu' # y = r x s (alu, no write back)
    cycles: [
      { # r x s into alu
        aluYNWE: 0
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
        regAluSel: 'r'
      }
    ]
  }
  {
    op: '011rsalu' # r = r x [s] (mem alu)
    cycles: [
      { # s to mar0
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
        memMar0NWE: 0
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 0
        regAluSel: 'r'
        memRamNOE: 0 # register
      }
      { # r x ram into alu
        memInstrImmToRamAddr: 0
        regAluSel: 'r'
        memRamNOE: 0 # register
        aluYNWE: 0
      }
      { # r x ram into alu (hold)
        memInstrImmToRamAddr: 0
        regAluSel: 'r'
      }
      { # alu into r
        aluNOE: 0
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
    ]
  }
  {
    op: '1100ralu' # r = r x [imm] (mem alu imm)
    cycles: [
      { # immediate -> ram
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
        regAluSel: 'r'
      }
      { # r x ram into alu
        memInstrImmToRamAddr: 1
        regAluSel: 'r'
        memRamNOE: 0 # register
        aluYNWE: 0
      }
      { # r x ram into alu (hold)
        memInstrImmToRamAddr: 1
        regAluSel: 'r'
      }
      { # alu into r
        aluNOE: 0
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
    ]
  }
  {
    op: '1101ralu' # y = r x [imm] ( mem alu imm)
    cycles: [
      { # immediate -> ram
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
        regAluSel: 'r'
      }
      { # r x ram into alu
        memInstrImmToRamAddr: 1
        regAluSel: 'r'
        memRamNOE: 0 # register
        aluYNWE: 0
      }
      { # r x ram into alu (hold)
        memInstrImmToRamAddr: 1
        regAluSel: 'r'
      }
    ]
  }
  {
    op: '1000ralu' # r = r x imm (alu)
    cycles: [
      { # immediate -> bus, reg -> alu
        memInstrNOE: 0
        regAluSel: 'r'
        aluYNWE: 0
      }
      { # alu into r
        aluNOE: 0
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
    ]
  }
  {
    op: '1001ralu' # y = r x imm (alu, no write back)
    cycles: [
      { # immediate -> bus, reg -> alu
        memInstrNOE: 0
        regAluSel: 'r'
        aluYNWE: 0
      }
    ]
  }

  # memory ops & io
  {
    op: '010000rs' # r = [s] (ldr)
    cycles: [
      { # s to mar0
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
        memMar0NWE: 0
        memInstrImmToRamAddr: 0
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 0
        memRamNOE: 0 # register
      }
      { # ram to r
        memInstrImmToRamAddr: 0
        memRamNOE: 0 # register
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
      { # ram address hold
        memInstrImmToRamAddr: 0
      }
    ]
  }
  {
    op: '1111000r' # r = [imm] (ldr)
    cycles: [
      {
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
      }
      { # ram to r
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
      { # ram address hold
        memInstrImmToRamAddr: 1
      }
    ]
  }
  {
    op: '1111010r' # r = [imm] (ldr) incremented sp
    cycles: [
      { # increment sp
        memSPUp: 1
        memSPNEn: 0
        memRamNOE: 0 # register
      }
      { # ram address setup
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
      }
      { # ram to r
        memInstrImmToRamAddr: 1
        memRamNOE: 0 # register
        reg0NWE: 'r'
        reg1NWE: '!r'
      }
      { # ram address setup
        memInstrImmToRamAddr: 0
      }
      { # decrement sp
        memSPUp: 0
        memSPNEn: 0
      }
    ]
  }
  {
    op: '010001rs' # [s] = r (str)
    cycles: [
      { # s to mar0
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
        memMar0NWE: 0
      }
      { # r into ram
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 0
        memRamNWE: 0 # register
      }
      { # ram write
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 0
      }
      { # hold ram inputs
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 0
      }
    ]
  }
  {
    op: '1111001r' # [imm] = r (str)
    cycles: [
      { # r into ram
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
        memRamNWE: 0 # register
      }
      { # r write
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
      }
      { # hold ram inputs
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
      }
    ]
  }
  {
    op: '1111011r' # [imm] = r (str) incremented sp
    cycles: [
      { # increment sp
        memSPUp: 1
        memSPNEn: 0
      }
      { # r into ram
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
        memRamNWE: 0 # register
      }
      { # ram write
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
      }
      { # hold ram inputs
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memInstrImmToRamAddr: 1
      }
      { # decrement sp
        memSPUp: 0
        memSPNEn: 0
      }
    ]
  }
  {
    op: '0100110r' # mar1 = r
    cycles: [
      { # r to mar1
        reg0BusNOE: 'r'
        reg1BusNOE: '!r'
        memMar1NWE: 0
      }
    ]
  }
  {
    op: '01001110' # mar1 = imm
    cycles: [
      { # imm to mar1
        memInstrNOE: 0
        memMar1NWE: 0
      }
    ]
  }
  {
    op: '010010rs' # r = s
    cycles: [
      { # s to bus to r
        reg0NWE: 'r'
        reg1NWE: '!r'
        reg0BusNOE: 's'
        reg1BusNOE: '!s'
      }
    ]
  }
  {
    op: '1111100r' # r = imm
    cycles: [
      { # imm to bus to r
        reg0NWE: 'r'
        reg1NWE: '!r'
        memInstrNOE: 0
      }
    ]
  }
  # jumpy with immediate
  {
    op: '1010flag' # pc := imm
    cycles: [
      { # imm to pc
        memPCNEn: 0
        memPCLoadN: 0
        memPCFromImm: 1
      }
    ]
  }
  # call / return
  {
    op: '10110000' # call
    cycles: [
      { # 0xffff into mar & increment sp
        memMar0NWE: 0
        memMar1NWE: 0
        busFFNOE: 0
        memSPUp: 1
        memSPNEn: 0
      }
      { # address + data setup
        memPCToRamN: 0
        memInstrImmToRamAddr: 0
        
        memRamNWE: 0 # register
      }
      { # store pc in ram[0xffff]
        memPCToRamN: 0
        memInstrImmToRamAddr: 0
      }
      { # address + data hold
        memPCToRamN: 0
        memInstrImmToRamAddr: 0
      }
      { # load pc from instrImm
        memPCLoadN: 0
        memPCNEn: 0
        memPCFromImm: 1
      }
    ]
  }
  {
    op: '10110001' # return
    cycles: [
      { # 0xffff into mar
        memMar0NWE: 0
        memMar1NWE: 0
        busFFNOE: 0
      }
      { # ram address setup
        memInstrImmToRamAddr: 0
        memPCFromImm: 0
        memRamNOE: 0 # register
      }
      { # load pc from ram
        memInstrImmToRamAddr: 0
        memPCFromImm: 0
        memRamNOE: 0 # register

        memPCLoadN: 0
        memPCNEn: 0
      }
      { # ram address hold
        memInstrImmToRamAddr: 0
        memPCFromImm: 0
      }
      { # decrement sp
        memSPUp: 0
        memSPNEn: 0
      }
    ]
  }
]