diff --git a/addition-gaps/cmd/test-addition/main.go b/addition-gaps/cmd/test-addition/main.go index f69e79e..6408784 100644 --- a/addition-gaps/cmd/test-addition/main.go +++ b/addition-gaps/cmd/test-addition/main.go @@ -3,8 +3,8 @@ package main import ( "encoding/binary" "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" "os" - "xcl" ) func main() { diff --git a/addition-gaps/main.go b/addition-gaps/main.go index d114dba..23c04bf 100644 --- a/addition-gaps/main.go +++ b/addition-gaps/main.go @@ -2,10 +2,10 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) // The Top function will be presented as a kernel diff --git a/addition/cmd/test-addition/main.go b/addition/cmd/test-addition/main.go index 21eea7a..447b4c7 100644 --- a/addition/cmd/test-addition/main.go +++ b/addition/cmd/test-addition/main.go @@ -3,8 +3,8 @@ package main import ( "encoding/binary" "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" "os" - "xcl" ) func main() { diff --git a/addition/main.go b/addition/main.go index 37ba548..cc3e17b 100644 --- a/addition/main.go +++ b/addition/main.go @@ -2,11 +2,11 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" "github.com/ReconfigureIO/addition" ) diff --git a/histogram-array/cmd/test-histogram/main.go b/histogram-array/cmd/test-histogram/main.go index de78559..f20166d 100644 --- a/histogram-array/cmd/test-histogram/main.go +++ b/histogram-array/cmd/test-histogram/main.go @@ -3,10 +3,10 @@ package main import ( "encoding/binary" "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" "log" "math/rand" "reflect" - "xcl" ) const ( diff --git a/histogram-array/main.go b/histogram-array/main.go index fb6cedc..73d0232 100644 --- a/histogram-array/main.go +++ b/histogram-array/main.go @@ -2,12 +2,17 @@ package main import ( // import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) +// calculate the bin for the histogram +func CalculateIndex(sample uint32) uint16 { + return uint16(sample) >> (16 - 9) +} + // magic identifier for exporting func Top( inputData uintptr, @@ -32,11 +37,9 @@ func Top( for ; length > 0; length-- { // First we'll pull of each sample from the channel sample := <-inputChan - // calculate the bin for the histogram - index := uint16(sample) >> (16 - 9) // And increment the value in that bin - histogram[uint(index)] += 1 + histogram[CalculateIndex(sample)] += 1 } data := make(chan uint32) diff --git a/histogram-array/main_test.go b/histogram-array/main_test.go new file mode 100644 index 0000000..7a6d990 --- /dev/null +++ b/histogram-array/main_test.go @@ -0,0 +1,17 @@ +package main + +import ( + "testing" + "testing/quick" +) + +func TestCalculateIndexDoesNotOutOfBounds(t *testing.T) { + // Check that we never generate an index out of bounds + f := func(x uint32) bool { + index := CalculateIndex(x) + return index < 512 + } + if err := quick.Check(f, nil); err != nil { + t.Error(err) + } +} diff --git a/histogram-parallel/cmd/test-histogram/main.go b/histogram-parallel/cmd/test-histogram/main.go index de78559..f20166d 100644 --- a/histogram-parallel/cmd/test-histogram/main.go +++ b/histogram-parallel/cmd/test-histogram/main.go @@ -3,10 +3,10 @@ package main import ( "encoding/binary" "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" "log" "math/rand" "reflect" - "xcl" ) const ( diff --git a/histogram-parallel/main.go b/histogram-parallel/main.go index 3a0fe1d..13d2cba 100644 --- a/histogram-parallel/main.go +++ b/histogram-parallel/main.go @@ -2,11 +2,11 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" - axiarbitrate "axi/arbitrate" - aximemory "axi/memory" - axiprotocol "axi/protocol" + axiarbitrate "github.com/ReconfigureIO/sdaccel/axi/arbitrate" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) // Magic identifier for exporting diff --git a/histogram/cmd/test-histogram/main.go b/histogram/cmd/test-histogram/main.go index de78559..f20166d 100644 --- a/histogram/cmd/test-histogram/main.go +++ b/histogram/cmd/test-histogram/main.go @@ -3,10 +3,10 @@ package main import ( "encoding/binary" "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" "log" "math/rand" "reflect" - "xcl" ) const ( diff --git a/histogram/main.go b/histogram/main.go index 9350689..f8d214b 100644 --- a/histogram/main.go +++ b/histogram/main.go @@ -2,10 +2,10 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) // Magic identifier for exporting diff --git a/memcopy/cmd/test-memcopy/main.go b/memcopy/cmd/test-memcopy/main.go index 8242b8e..936a850 100644 --- a/memcopy/cmd/test-memcopy/main.go +++ b/memcopy/cmd/test-memcopy/main.go @@ -2,12 +2,12 @@ package main import ( "encoding/binary" + "github.com/ReconfigureIO/sdaccel/xcl" "log" "math/rand" "reflect" "testing/quick" "time" - "xcl" ) const DATA_WIDTH = 12 diff --git a/memcopy/main.go b/memcopy/main.go index ecd1945..b288e97 100644 --- a/memcopy/main.go +++ b/memcopy/main.go @@ -2,10 +2,10 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) // Magic identifier for exporting diff --git a/memtest/cmd/memtest/main.go b/memtest/cmd/memtest/main.go index c7533b4..d5cc8c9 100644 --- a/memtest/cmd/memtest/main.go +++ b/memtest/cmd/memtest/main.go @@ -1,8 +1,8 @@ package main import ( + "github.com/ReconfigureIO/sdaccel/xcl" "log" - "xcl" ) func main() { diff --git a/memtest/main.go b/memtest/main.go index d123af6..396958d 100644 --- a/memtest/main.go +++ b/memtest/main.go @@ -2,8 +2,8 @@ package main import ( // import the entire framework (including bundled verilog) - _ "sdaccel" - "sdaccel/memory" + _ "github.com/ReconfigureIO/sdaccel" + "github.com/ReconfigureIO/sdaccel/axi/memory" ) // magic identifier for exporting diff --git a/template/main.go b/template/main.go index 013087c..bec138d 100644 --- a/template/main.go +++ b/template/main.go @@ -2,11 +2,11 @@ package main import ( // Import the entire framework (including bundled verilog) - _ "sdaccel" + _ "github.com/ReconfigureIO/sdaccel" // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) func Top( diff --git a/tutorial3_examples/multiply-array/cmd/test-multiply-array/main.go b/tutorial3_examples/multiply-array/cmd/test-multiply-array/main.go index 6db810e..6633c6e 100644 --- a/tutorial3_examples/multiply-array/cmd/test-multiply-array/main.go +++ b/tutorial3_examples/multiply-array/cmd/test-multiply-array/main.go @@ -1,68 +1,68 @@ package main import ( - "encoding/binary" - "xcl" - "fmt" + "encoding/binary" + "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" ) func main() { - // Allocate a 'world' for interacting with kernels - world := xcl.NewWorld() - defer world.Release() + // Allocate a 'world' for interacting with kernels + world := xcl.NewWorld() + defer world.Release() - // Import the kernel. - // Right now these two identifiers are hard coded as an output from the build process - krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") - defer krnl.Release() + // Import the kernel. + // Right now these two identifiers are hard coded as an output from the build process + krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") + defer krnl.Release() - // Create/get data and pass arguments to the kernel as required. These could be small pieces of data, - // pointers to memory, data lengths so the Kernel knows what to expect. This all depends on your project. - // We have passed three arguments here, you can pass more as neccessary + // Create/get data and pass arguments to the kernel as required. These could be small pieces of data, + // pointers to memory, data lengths so the Kernel knows what to expect. This all depends on your project. + // We have passed three arguments here, you can pass more as neccessary - // make an array to send to the kernel for processing - input := make([]uint32, 10) + // make an array to send to the kernel for processing + input := make([]uint32, 10) - // seed it with incrementing values - for i, _ := range input { - input[i] = uint32(i) - } + // seed it with incrementing values + for i, _ := range input { + input[i] = uint32(i) + } - // Create space in shared memory for our array input - buff := world.Malloc(xcl.ReadOnly, uint(binary.Size(input))) - defer buff.Free() + // Create space in shared memory for our array input + buff := world.Malloc(xcl.ReadOnly, uint(binary.Size(input))) + defer buff.Free() - // Create a variable to hold the output from the FPGA - var output [10]uint32 + // Create a variable to hold the output from the FPGA + var output [10]uint32 - // Create space in the shared memory for the output from the FPGA - outputBuff := world.Malloc(xcl.ReadWrite, uint(binary.Size(output))) - defer outputBuff.Free() + // Create space in the shared memory for the output from the FPGA + outputBuff := world.Malloc(xcl.ReadWrite, uint(binary.Size(output))) + defer outputBuff.Free() - // write our input to the shared memory at the location we specified previously - binary.Write(buff.Writer(), binary.LittleEndian, &input) + // write our input to the shared memory at the location we specified previously + binary.Write(buff.Writer(), binary.LittleEndian, &input) - // zero out output space - binary.Write(outputBuff.Writer(), binary.LittleEndian, &output) + // zero out output space + binary.Write(outputBuff.Writer(), binary.LittleEndian, &output) - // Send the location of the input array as the first argument - krnl.SetMemoryArg(0, buff) - // Send the location the FPGA should put the result as the second argument - krnl.SetMemoryArg(1, outputBuff) - // Send the length of the input array, so the kernel knows what to expect, as the third argument - krnl.SetArg(2, uint32(len(input))) + // Send the location of the input array as the first argument + krnl.SetMemoryArg(0, buff) + // Send the location the FPGA should put the result as the second argument + krnl.SetMemoryArg(1, outputBuff) + // Send the length of the input array, so the kernel knows what to expect, as the third argument + krnl.SetArg(2, uint32(len(input))) - // Run the kernel with the supplied arguments. This is the same for all projects. - // The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current - // underlying technology. - krnl.Run(1, 1, 1) + // Run the kernel with the supplied arguments. This is the same for all projects. + // The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current + // underlying technology. + krnl.Run(1, 1, 1) - // Display/use the results returned from the FPGA as required! + // Display/use the results returned from the FPGA as required! - binary.Read(outputBuff.Reader(), binary.LittleEndian, &output); + binary.Read(outputBuff.Reader(), binary.LittleEndian, &output) - for _, val := range output { - print(val) - } + for _, val := range output { + print(val) + } } diff --git a/tutorial3_examples/multiply-array/main.go b/tutorial3_examples/multiply-array/main.go index c3289ea..1f9f9d7 100644 --- a/tutorial3_examples/multiply-array/main.go +++ b/tutorial3_examples/multiply-array/main.go @@ -1,48 +1,48 @@ package main import ( - // Import the entire framework (including bundled verilog) - _ "sdaccel" + // Import the entire framework (including bundled verilog) + _ "github.com/ReconfigureIO/sdaccel" - // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + // Use the new AXI protocol package + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) func Top( - // Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type - // to expect or pass single integers directly to the kernel by sending them to the FPGA's control register - - inputData uintptr, - outputData uintptr, - length uint32, - - // Set up channels for interacting with the shared memory - memReadAddr chan<- axiprotocol.Addr, - memReadData <-chan axiprotocol.ReadData, - - memWriteAddr chan<- axiprotocol.Addr, - memWriteData chan<- axiprotocol.WriteData, - memWriteResp <-chan axiprotocol.WriteResp) { - - // Do whatever needs doing with the data from the host - - // Read all the input data into a channel - inputChan := make(chan uint32) - go aximemory.ReadBurstUInt32( - memReadAddr, memReadData, true, inputData, length, inputChan) - - // Create a channel for the result of the calculation - transformedChan := make(chan uint32) - // multiply each element of the input channel by 2 and send to the channel we just made to hold the result - go func(){ - // no need to stop here, which will save us some clocks checking - for { - transformedChan <- (<-inputChan) * 2 - } - }() - - // Write transformed results back to memory - aximemory.WriteBurstUInt32( - memWriteAddr, memWriteData, memWriteResp, true, outputData, length, transformedChan) + // Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type + // to expect or pass single integers directly to the kernel by sending them to the FPGA's control register + + inputData uintptr, + outputData uintptr, + length uint32, + + // Set up channels for interacting with the shared memory + memReadAddr chan<- axiprotocol.Addr, + memReadData <-chan axiprotocol.ReadData, + + memWriteAddr chan<- axiprotocol.Addr, + memWriteData chan<- axiprotocol.WriteData, + memWriteResp <-chan axiprotocol.WriteResp) { + + // Do whatever needs doing with the data from the host + + // Read all the input data into a channel + inputChan := make(chan uint32) + go aximemory.ReadBurstUInt32( + memReadAddr, memReadData, true, inputData, length, inputChan) + + // Create a channel for the result of the calculation + transformedChan := make(chan uint32) + // multiply each element of the input channel by 2 and send to the channel we just made to hold the result + go func() { + // no need to stop here, which will save us some clocks checking + for { + transformedChan <- (<-inputChan) * 2 + } + }() + + // Write transformed results back to memory + aximemory.WriteBurstUInt32( + memWriteAddr, memWriteData, memWriteResp, true, outputData, length, transformedChan) } diff --git a/tutorial3_examples/multiply1/cmd/test-multiply1/main.go b/tutorial3_examples/multiply1/cmd/test-multiply1/main.go index 68171b5..94a0081 100644 --- a/tutorial3_examples/multiply1/cmd/test-multiply1/main.go +++ b/tutorial3_examples/multiply1/cmd/test-multiply1/main.go @@ -1,44 +1,44 @@ package main import ( - "encoding/binary" - "xcl" - "fmt" + "encoding/binary" + "fmt" + "github.com/ReconfigureIO/sdaccel/xcl" ) func main() { - // Allocate a 'world' for interacting with kernels - world := xcl.NewWorld() - defer world.Release() - - // Import the kernel. - // Right now these two identifiers are hard coded as an output from the build process - krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") - defer krnl.Release() - - // Allocate a space in the shared memory to store the results from the FPGA - // The output is a uint32, so we need 4 bytes to store it - buff := world.Malloc(xcl.WriteOnly, 4) - defer buff.Free() - - // Pass the arguments to the kernel. These could be small pieces of data, pointers to - // memory, data lengths so the Kernel knows what to expect. This all depends on your project. - - // First argument - krnl.SetArg(0, 1) - // Second argument - krnl.SetMemoryArg(1, buff) - - // Run the kernel with the supplied arguments. This is the same for all projects. - // The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current - // underlying technology. - krnl.Run(1, 1, 1) - - // Display/use the results returned from the FPGA as required! - var output uint32 - binary.Read(buff.Reader(), binary.LittleEndian, &output); - - // Print the value we got from the FPGA - fmt.Printf("%d\n", output) + // Allocate a 'world' for interacting with kernels + world := xcl.NewWorld() + defer world.Release() + + // Import the kernel. + // Right now these two identifiers are hard coded as an output from the build process + krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") + defer krnl.Release() + + // Allocate a space in the shared memory to store the results from the FPGA + // The output is a uint32, so we need 4 bytes to store it + buff := world.Malloc(xcl.WriteOnly, 4) + defer buff.Free() + + // Pass the arguments to the kernel. These could be small pieces of data, pointers to + // memory, data lengths so the Kernel knows what to expect. This all depends on your project. + + // First argument + krnl.SetArg(0, 1) + // Second argument + krnl.SetMemoryArg(1, buff) + + // Run the kernel with the supplied arguments. This is the same for all projects. + // The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current + // underlying technology. + krnl.Run(1, 1, 1) + + // Display/use the results returned from the FPGA as required! + var output uint32 + binary.Read(buff.Reader(), binary.LittleEndian, &output) + + // Print the value we got from the FPGA + fmt.Printf("%d\n", output) } diff --git a/tutorial3_examples/multiply1/main.go b/tutorial3_examples/multiply1/main.go index 1ba27c3..977fb4a 100644 --- a/tutorial3_examples/multiply1/main.go +++ b/tutorial3_examples/multiply1/main.go @@ -1,38 +1,38 @@ package main import ( - // Import the entire framework (including bundled verilog) - _ "sdaccel" + // Import the entire framework (including bundled verilog) + _ "github.com/ReconfigureIO/sdaccel" - // Use the new AXI protocol package - aximemory "axi/memory" - axiprotocol "axi/protocol" + // Use the new AXI protocol package + aximemory "github.com/ReconfigureIO/sdaccel/axi/memory" + axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol" ) func Top( - // Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type - // to expect or pass single integers directly to the kernel by sending them to the FPGA's control register + // Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type + // to expect or pass single integers directly to the kernel by sending them to the FPGA's control register - a uint32, - addr uintptr, + a uint32, + addr uintptr, - // Set up channels for interacting with the shared memory - memReadAddr chan<- axiprotocol.Addr, - memReadData <-chan axiprotocol.ReadData, + // Set up channels for interacting with the shared memory + memReadAddr chan<- axiprotocol.Addr, + memReadData <-chan axiprotocol.ReadData, - memWriteAddr chan<- axiprotocol.Addr, - memWriteData chan<- axiprotocol.WriteData, - memWriteResp <-chan axiprotocol.WriteResp) { + memWriteAddr chan<- axiprotocol.Addr, + memWriteData chan<- axiprotocol.WriteData, + memWriteResp <-chan axiprotocol.WriteResp) { - // Since we're not reading anything from memory, disable those reads - go axiprotocol.ReadDisable(memReadAddr, memReadData) + // Since we're not reading anything from memory, disable those reads + go axiprotocol.ReadDisable(memReadAddr, memReadData) - // Do whatever needs doing with the data from the host + // Do whatever needs doing with the data from the host - // Multiply incoming data by 2 - val := a * 2 + // Multiply incoming data by 2 + val := a * 2 - // Write the result to the location in shared memory as requested by the host - aximemory.WriteUInt32( - memWriteAddr, memWriteData, memWriteResp, true, addr, uint32(val)) + // Write the result to the location in shared memory as requested by the host + aximemory.WriteUInt32( + memWriteAddr, memWriteData, memWriteResp, true, addr, uint32(val)) }