replace magic libraries with open-source ones

Author: CampGareth

addition-gaps/cmd/test-addition/main.go

@@ -3,8 +3,8 @@ package main
 import (
 	"encoding/binary"
 	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"os"
-	"xcl"
 )
 
 func main() {

addition-gaps/main.go

@@ -2,10 +2,10 @@ package main
 
 import (
 	// Import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 // The Top function will be presented as a kernel

addition/cmd/test-addition/main.go

@@ -3,8 +3,8 @@ package main
 import (
 	"encoding/binary"
 	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"os"
-	"xcl"
 )
 
 func main() {

addition/main.go

@@ -2,11 +2,11 @@ package main
 
 import (
 	// Import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 
 	// Use the new AXI protocol package
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 
 	"github.com/ReconfigureIO/addition"
 )

histogram-array/cmd/test-histogram/main.go

@@ -3,10 +3,10 @@ package main
 import (
 	"encoding/binary"
 	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"log"
 	"math/rand"
 	"reflect"
-	"xcl"
 )
 
 const (

histogram-array/main.go

@@ -2,10 +2,10 @@ package main
 
 import (
 	// import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 	// Use the new AXI protocol package
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 // magic identifier for exporting

histogram-parallel/cmd/test-histogram/main.go

@@ -3,10 +3,10 @@ package main
 import (
 	"encoding/binary"
 	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"log"
 	"math/rand"
 	"reflect"
-	"xcl"
 )
 
 const (

histogram-parallel/main.go

@@ -2,11 +2,11 @@ package main
 
 import (
 	// Import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 
-	axiarbitrate "axi/arbitrate"
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	axiarbitrate "github.com/ReconfigureIO/sdaccel/axi/arbitrate"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 // Magic identifier for exporting

histogram/cmd/test-histogram/main.go

@@ -3,10 +3,10 @@ package main
 import (
 	"encoding/binary"
 	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"log"
 	"math/rand"
 	"reflect"
-	"xcl"
 )
 
 const (

histogram/main.go

@@ -2,10 +2,10 @@ package main
 
 import (
 	// Import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 	// Use the new AXI protocol package
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 // Magic identifier for exporting

memcopy/cmd/test-memcopy/main.go

@@ -2,12 +2,12 @@ package main
 
 import (
 	"encoding/binary"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"log"
 	"math/rand"
 	"reflect"
 	"testing/quick"
 	"time"
-	"xcl"
 )
 
 const DATA_WIDTH = 12

memcopy/main.go

@@ -2,10 +2,10 @@ package main
 
 import (
 	// Import the entire framework (including bundled verilog)
-	_ "sdaccel"
+	_ "github.com/ReconfigureIO/sdaccel"
 	// Use the new AXI protocol package
-	aximemory "axi/memory"
-	axiprotocol "axi/protocol"
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 // Magic identifier for exporting

memtest/cmd/memtest/main.go

@@ -1,8 +1,8 @@
 package main
 
 import (
+	"github.com/ReconfigureIO/sdaccel/xcl"
 	"log"
-	"xcl"
 )
 
 func main() {

memtest/main.go

@@ -2,8 +2,8 @@ package main
 
 import (
 	// import the entire framework (including bundled verilog)
-	_ "sdaccel"
-	"sdaccel/memory"
+	_ "github.com/ReconfigureIO/sdaccel"
+	"github.com/ReconfigureIO/sdaccel/axi/memory"
 )
 
 // magic identifier for exporting

template/main.go

@@ -2,11 +2,11 @@ package main
 
 import (
     // Import the entire framework (including bundled verilog)
-    _ "sdaccel"
+    _ "github.com/ReconfigureIO/sdaccel"
 
     // Use the new AXI protocol package
-    aximemory "axi/memory"
-    axiprotocol "axi/protocol"
+    aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+    axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 func Top(

tutorial3_examples/multiply-array/cmd/test-multiply-array/main.go

@@ -1,68 +1,68 @@
 package main
 
 import (
-    "encoding/binary"
-    "xcl"
-    "fmt"
+	"encoding/binary"
+	"fmt"
+	"github.com/ReconfigureIO/sdaccel/xcl"
 )
 
 func main() {
-    // Allocate a 'world' for interacting with kernels
-    world := xcl.NewWorld()
-    defer world.Release()
+	// Allocate a 'world' for interacting with kernels
+	world := xcl.NewWorld()
+	defer world.Release()
 
-    // Import the kernel.
-    // Right now these two identifiers are hard coded as an output from the build process
-    krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1")
-    defer krnl.Release()
+	// Import the kernel.
+	// Right now these two identifiers are hard coded as an output from the build process
+	krnl := world.Import("kernel_test").GetKernel("reconfigure_io_sdaccel_builder_stub_0_1")
+	defer krnl.Release()
 
-    // Create/get data and pass arguments to the kernel as required. These could be small pieces of data,
-    // pointers to memory, data lengths so the Kernel knows what to expect. This all depends on your project.
-    // We have passed three arguments here, you can pass more as neccessary
+	// Create/get data and pass arguments to the kernel as required. These could be small pieces of data,
+	// pointers to memory, data lengths so the Kernel knows what to expect. This all depends on your project.
+	// We have passed three arguments here, you can pass more as neccessary
 
-    // make an array to send to the kernel for processing
-    input := make([]uint32, 10)
+	// make an array to send to the kernel for processing
+	input := make([]uint32, 10)
 
-	  // seed it with incrementing values
-  	for i, _ := range input {
-  		input[i] = uint32(i)
-  	}
+	// seed it with incrementing values
+	for i, _ := range input {
+		input[i] = uint32(i)
+	}
 
-    // Create space in shared memory for our array input
-  	buff := world.Malloc(xcl.ReadOnly, uint(binary.Size(input)))
-  	defer buff.Free()
+	// Create space in shared memory for our array input
+	buff := world.Malloc(xcl.ReadOnly, uint(binary.Size(input)))
+	defer buff.Free()
 
-    // Create a variable to hold the output from the FPGA
-  	var output [10]uint32
+	// Create a variable to hold the output from the FPGA
+	var output [10]uint32
 
-  	// Create space in the shared memory for the output from the FPGA
-  	outputBuff := world.Malloc(xcl.ReadWrite, uint(binary.Size(output)))
-  	defer outputBuff.Free()
+	// Create space in the shared memory for the output from the FPGA
+	outputBuff := world.Malloc(xcl.ReadWrite, uint(binary.Size(output)))
+	defer outputBuff.Free()
 
-  	// write our input to the shared memory at the location we specified previously
-  	binary.Write(buff.Writer(), binary.LittleEndian, &input)
+	// write our input to the shared memory at the location we specified previously
+	binary.Write(buff.Writer(), binary.LittleEndian, &input)
 
-  	// zero out output space
-  	binary.Write(outputBuff.Writer(), binary.LittleEndian, &output)
+	// zero out output space
+	binary.Write(outputBuff.Writer(), binary.LittleEndian, &output)
 
-    // Send the location of the input array as the first argument
-    krnl.SetMemoryArg(0, buff)
-    // Send the location the FPGA should put the result as the second argument
-    krnl.SetMemoryArg(1, outputBuff)
-    // Send the length of the input array, so the kernel knows what to expect, as the third argument
-    krnl.SetArg(2, uint32(len(input)))
+	// Send the location of the input array as the first argument
+	krnl.SetMemoryArg(0, buff)
+	// Send the location the FPGA should put the result as the second argument
+	krnl.SetMemoryArg(1, outputBuff)
+	// Send the length of the input array, so the kernel knows what to expect, as the third argument
+	krnl.SetArg(2, uint32(len(input)))
 
-    // Run the kernel with the supplied arguments. This is the same for all projects.
-    // The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current
-    // underlying technology.
-    krnl.Run(1, 1, 1)
+	// Run the kernel with the supplied arguments. This is the same for all projects.
+	// The arguments ``(1, 1, 1)`` relate to x, y, z co-ordinates and correspond to our current
+	// underlying technology.
+	krnl.Run(1, 1, 1)
 
-    // Display/use the results returned from the FPGA as required!
+	// Display/use the results returned from the FPGA as required!
 
-    binary.Read(outputBuff.Reader(), binary.LittleEndian, &output);
+	binary.Read(outputBuff.Reader(), binary.LittleEndian, &output)
 
-    for _, val := range output {
-      print(val)
-    }
+	for _, val := range output {
+		print(val)
+	}
 
 }

tutorial3_examples/multiply-array/main.go

@@ -1,48 +1,48 @@
 package main
 
 import (
-    // Import the entire framework (including bundled verilog)
-    _ "sdaccel"
+	// Import the entire framework (including bundled verilog)
+	_ "github.com/ReconfigureIO/sdaccel"
 
-    // Use the new AXI protocol package
-    aximemory "axi/memory"
-    axiprotocol "axi/protocol"
+	// Use the new AXI protocol package
+	aximemory "github.com/ReconfigureIO/sdaccel/axi/memory"
+	axiprotocol "github.com/ReconfigureIO/sdaccel/axi/protocol"
 )
 
 func Top(
-    // Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type
-    // to expect or pass single integers directly to the kernel by sending them to the FPGA's control register
-
-    inputData uintptr,
-    outputData uintptr,
-    length uint32,
-
-    // Set up channels for interacting with the shared memory
-    memReadAddr chan<- axiprotocol.Addr,
-    memReadData <-chan axiprotocol.ReadData,
-
-    memWriteAddr chan<- axiprotocol.Addr,
-    memWriteData chan<- axiprotocol.WriteData,
-    memWriteResp <-chan axiprotocol.WriteResp) {
-
-    // Do whatever needs doing with the data from the host
-
-    // Read all the input data into a channel
-    inputChan := make(chan uint32)
-    go aximemory.ReadBurstUInt32(
-        memReadAddr, memReadData, true, inputData, length, inputChan)
-
-    // Create a channel for the result of the calculation
-    transformedChan := make(chan uint32)
-    // multiply each element of the input channel by 2 and send to the channel we just made to hold the result
-    go func(){
-        // no need to stop here, which will save us some clocks checking
-        for {
-            transformedChan <- (<-inputChan) * 2
-        }
-    }()
-    
-    // Write transformed results back to memory
-    aximemory.WriteBurstUInt32(
-        memWriteAddr, memWriteData, memWriteResp, true, outputData, length, transformedChan)
+	// Specify inputs and outputs to the kernel. Tell the kernel where to find data in shared memory, what data type
+	// to expect or pass single integers directly to the kernel by sending them to the FPGA's control register
+
+	inputData uintptr,
+	outputData uintptr,
+	length uint32,
+
+	// Set up channels for interacting with the shared memory
+	memReadAddr chan<- axiprotocol.Addr,
+	memReadData <-chan axiprotocol.ReadData,
+
+	memWriteAddr chan<- axiprotocol.Addr,
+	memWriteData chan<- axiprotocol.WriteData,
+	memWriteResp <-chan axiprotocol.WriteResp) {
+
+	// Do whatever needs doing with the data from the host
+
+	// Read all the input data into a channel
+	inputChan := make(chan uint32)
+	go aximemory.ReadBurstUInt32(
+		memReadAddr, memReadData, true, inputData, length, inputChan)
+
+	// Create a channel for the result of the calculation
+	transformedChan := make(chan uint32)
+	// multiply each element of the input channel by 2 and send to the channel we just made to hold the result
+	go func() {
+		// no need to stop here, which will save us some clocks checking
+		for {
+			transformedChan <- (<-inputChan) * 2
+		}
+	}()
+
+	// Write transformed results back to memory
+	aximemory.WriteBurstUInt32(
+		memWriteAddr, memWriteData, memWriteResp, true, outputData, length, transformedChan)
 }