- Simulations now post an FPGA resource utilisation report to platform
- Use new compiler update, which introduces ll2ll LLVM optimisation phase (eTeak #661)
- Removed support for reco-check under Windows to simplify the build process, since it is not being actively used by any customers (#238, eTeak #668)
- Phased migration to new compiler.
- Use new compiler as the default for the histogram array example (#232)
- Add additional reporting for post P&R system clock speed (#233)
- Added support for intermediate graph generation
- Added a 15 minute time limit for simulation
- Added a 5 hour time limit for builds
- Fixed usage reports crashing when only half a BRAM block was used
- Bump compiler to v0.7.0
- Bump compiler to v0.6.0
- Add
MemoryReader&MemoryWritertoxclwith correspondingio.Reader&io.Writerinstances.
- Fix possible segfaults in
xcl.
- Fix compatibility for latest compiler.
* Update compiler to v0.5.0
* Fix reliability of build process by reducing network calls
- Display builds that were being filtered
- Work with more Jarvice accounts
- Initial implementation.
- Include
reco-jarvicetool for deploying workloads on https://xilinx-cloud.jarvice.com