ldd.adoc

th.ldd

Synopsis

Load two 64-bit values from memory into two GPRs.

Mnemonic

th.ldd rd1, rd2, (rs1), imm2, 4

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd1' },
    { bits:  3, name: 0x4, attr: ['Mem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'rd2' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x1f },
]}

Description

This instruction loads two 64-bit values into the two GP registers rd1 and rd2 from the address rs1 + (zero_extend(imm2) << 4).

The encoding of this instruction with equal rd1, rd2 and rs1 is reserved.

Note, that there is no atomicity guarantee for this instruction. I.e., an implementation can realize this instruction in form of two memory transactions and an exception can be handled in-between, in which case the whole instruction will be re-executed.

Operation

if (rs1 != rd1 && rs1 != rd2 && rd1 != rd2) {
    addr := rs1 + (zero_extend(imm2) << 4)
    tmp1 := mem[addr+7:addr]
    tmp2 := mem[addr+15:addr+8]
    (reg[rd1], reg[rd2]) := (tmp1, tmp2)
}

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that two corresponding LD instructions would trigger.

Included in

Extension
XTheadMemPair ([xtheadmempair])