From a18c801634acfb5a367abf955db7d056542307c9 Mon Sep 17 00:00:00 2001 From: majin2020 Date: Thu, 19 Oct 2023 20:27:17 +0800 Subject: [PATCH] Add T-Head VECTOR vendor extension. --- docinfo.adoc | 1 + intro.adoc | 1 + xthead.adoc | 1 + xtheadvector.adoc | 29 +++++++++++++++++++++++++++++ 4 files changed, 32 insertions(+) create mode 100644 xtheadvector.adoc diff --git a/docinfo.adoc b/docinfo.adoc index 467c522..2008e63 100644 --- a/docinfo.adoc +++ b/docinfo.adoc @@ -20,3 +20,4 @@ The list below includes all contributors to this document in alphabetical order: * Philipp Tomsich * Yunhai Shang < yunhai@linux.alibaba.com> * Zhiwei Liu +* Jin Ma diff --git a/intro.adoc b/intro.adoc index 25ba00b..7617894 100644 --- a/intro.adoc +++ b/intro.adoc @@ -37,6 +37,7 @@ The collection consists of the following ISA extensions: * `XTheadFmv` provides double floating-point high-bit data transmission instructions. * `XTheadInt` provides acceleration interruption instructions. * `XTheadVdot` provides instructions for vector dot. +* `XTheadVector` provides instructions for thead vector. === Dependencies to standard extensions diff --git a/xthead.adoc b/xthead.adoc index 33af5ee..13f8e4b 100644 --- a/xthead.adoc +++ b/xthead.adoc @@ -47,3 +47,4 @@ include::xtheadmac.adoc[] include::xtheadfmv.adoc[] include::xtheadint.adoc[] include::xtheadvdot.adoc[] +include::xtheadvector.adoc[] diff --git a/xtheadvector.adoc b/xtheadvector.adoc new file mode 100644 index 0000000..776aca1 --- /dev/null +++ b/xtheadvector.adoc @@ -0,0 +1,29 @@ +[#xtheadvector] +== Vector implementation of THEAD. + +[NOTE,caption=Frozen] +The `XTheadVector` extension is `stable`. + +Extension version: 1.0. + +The `XTheadVector` extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the `TheadVector` instructions overlaps with those of the `V` extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the `XTheadVector` extension and the `V` extension are in conflict. In other words, tools should not allow to enable the `TheadVector` extension and the `V` extension at the same time and should report an error if both are enabled by the user. + +The `XTheadVector` extension adds 32 vector registers, and six unprivileged CSRs (`th.vstart`, `th.vxsat`, `th.vxrm`, `th.vl`, `th.vtype` and `th.vlenb`) , which also overlap with those of the `V` extension (`vstart`, `vxsat`, `vxrm`, `vl`, `vtype` and `vlenb`). + +The `XTheadVector` extension is only available if and only if all of the following conditions are met: + +* The value of the `mvendor` CSR is `0x5b7` ('T-Head') +* Bit 21 of the `misa` CSR is `1` ('V') +* The value of the `mimpid` CSR is `0` + +These conditions not only reliably identify existing CPUs with XTheadVector (C906V, C920, and R920), +but also ensure that future T-Head CPUs without XTheadVector won't be falsely detected (in this case `mimpid` won't be `0`). + +The instructions set of `XTheadVector` overlaps with the Vector Extension, v0.7.1(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1). But here are some changes: + +* In order to facilitate VLEN calculation, The `XTheadVector` extension adopts the definition of the `V` extension to add VLENB unprivileged register `th.vlenb`. +* The five unprivileged CSRs `vstart`, `vxsat`, `vxrm`, `vl` and `vtype` are prefixed with `th.`, for example, `vstart` is changed to `th.vstart`. +* All instructions are prefixed with `th.`, for example, `vmv.v.v` is changed to `th.vmv.v.v`. +* The extension `Zvamo` is renamed to `XTheadZvamo`. +* The extension `Zvlsseg` (chapter 7.8) is not a subextension but a mandatory part of XTheadVector. +* The Chapter `19. Divided Element Extension ('Zvediv')` is not part of XTheadVector.