README.txt

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This repository presents a verification test case for a master implementation of the Two-Wire Serial Register Interface based on Systemverilog Object Oriented concepts and also UVM. The general architecture and implementation of the code has been taken from the UVM primer (Ray Salemi):

https://github.com/rdsalemi/uvmprimer

and also partly from:

http://www.asic-world.com/examples/systemverilog/uart.html

However the presented verification code in this test case is manipulated to be fitted for the special use case of the Two-Wire Serial Register Interface.

Thanks
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This work was supported by:
PICSy project at Potsdam Universitaet
https://www.cs.uni-potsdam.de/techinf/projects/picsy/

also also:

Leibniz-Institut fuer Agrartechnik Potsdam-Bornim e.V.
https://www.atb-potsdam.de/de/institut/fachabteilungen/technik-im-pflanzenbau