Release desktop

Author: Samuelopez-ansys

examples/01-HFSS3DLayout/01_power_integrity.py

@@ -1,11 +1,11 @@
 # # HFSS 3D Layout: Power Integrity Analysis
-# This example shows how to use the electronics database (EDB) for power integrity analysis. The 
+# This example shows how to use the electronics database (EDB) for power integrity analysis. The
 # EDB will be loaded into HFSS 3D Layout for analysis and post-processing.
 # - Set up EDB
 #     - Assign S-parameter model to components
 #     - Create pin groups
 #     - Create ports
-#     - Create SIwave SYZ anaylsis
+#     - Create SIwave SYZ analysis
 #     - Create cutout
 # - Import EDB into HFSS 3D Layout
 #     - Analyze
@@ -14,14 +14,16 @@
 # ## Preparation
 # Import the required packages
 
+import json
+
 # +
 import os
-import json
 import tempfile
 import time
-from pyaedt import Edb
-from pyaedt import Hfss3dLayout
+
+from pyaedt import Edb, Hfss3dLayout
 from pyaedt.downloads import download_file
+
 try:
     from ansys.pyaedt.examples.constants import AEDT_VERSION
 except:
@@ -34,9 +36,7 @@
 # Download the example PCB data.
 
 temp_folder = tempfile.TemporaryDirectory(suffix=".ansys")
-aedb = download_file(
-    source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name
-)
+aedb = download_file(source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name)
 download_file(
     source="touchstone", name="GRM32_DC0V_25degC_series.s2p", destination=temp_folder.name
 )
@@ -48,16 +48,14 @@
 
 cfg = dict()
 
-# In this example, we are going to assign S-parameter models to capacitors. 
+# In this example, we are going to assign S-parameter models to capacitors.
 # The first step is to use the "general" key to specify where the S-parameter files can be found.
 
-cfg["general"] = {
-    "s_parameter_library": os.path.join(temp_folder.name, "touchstone")
-}
+cfg["general"] = {"s_parameter_library": os.path.join(temp_folder.name, "touchstone")}
 
-# ## Assign model to capactitors. 
+# ## Assign model to capactitors.
 # In this example, the model "GRM32_DC0V_25degC_series.s2p" is assigned to capacitors C3 and C4, which share the same component part number.
-# When "apply_to_all" is ``True``, all components having the part number "CAPC3216X180X20ML20" will be assigned the S-parameter model. 
+# When "apply_to_all" is ``True``, all components having the part number "CAPC3216X180X20ML20" will be assigned the S-parameter model.
 
 cfg["s_parameters"] = [
     {
@@ -67,27 +65,17 @@
         "apply_to_all": False,
         "components": ["C110", "C206"],
         "reference_net": "GND",
-        "reference_net_per_component": {
-            "C110": "GND"
-        }
+        "reference_net_per_component": {"C110": "GND"},
     }
 ]
 
 # ## Create pin groups.
-# In this example, the listed pins on component U2 are combined into two pin groups. 
+# In this example, the listed pins on component U2 are combined into two pin groups.
 # Pins can be grouped explicitly by the pin name or pin groups can be assigned by net name using the "net" key as shown here:
 
 cfg["pin_groups"] = [
-    {
-        "name": "PIN_GROUP_1",
-        "reference_designator": "U1",
-        "pins": ["AD14", "AD15", "AD16", "AD17"]
-    },
-    {
-        "name": "PIN_GROUP_2",
-        "reference_designator": "U1",
-        "net": "GND"
-    }
+    {"name": "PIN_GROUP_1", "reference_designator": "U1", "pins": ["AD14", "AD15", "AD16", "AD17"]},
+    {"name": "PIN_GROUP_2", "reference_designator": "U1", "net": "GND"},
 ]
 
 # ## Create ports
@@ -98,12 +86,8 @@
         "name": "port1",
         "reference_designator": "U1",
         "type": "circuit",
-        "positive_terminal": {
-            "pin_group": "PIN_GROUP_1"
-        },
-        "negative_terminal": {
-            "pin_group": "PIN_GROUP_2"
-        }
+        "positive_terminal": {"pin_group": "PIN_GROUP_1"},
+        "negative_terminal": {"pin_group": "PIN_GROUP_2"},
     }
 ]
 
@@ -120,15 +104,10 @@
                 "name": "Sweep1",
                 "type": "Interpolation",
                 "frequencies": [
-                    {
-                        "distribution": "log scale",
-                        "start": 1e6,
-                        "stop": 1e9,
-                        "samples": 20
-                    }
-                ]
+                    {"distribution": "log scale", "start": 1e6, "stop": 1e9, "samples": 20}
+                ],
             }
-        ]
+        ],
     }
 ]
 
@@ -159,7 +138,7 @@
         "maximum_iterations": 10,
         "preserve_components_with_model": False,
         "simple_pad_check": True,
-        "keep_lines_as_path": False
+        "keep_lines_as_path": False,
     }
 }
 
@@ -190,10 +169,7 @@
 # ### Load edb into HFSS 3D Layout.
 
 h3d = Hfss3dLayout(
-    aedb,
-    specified_version=AEDT_VERSION,
-    non_graphical=NG_MODE,
-    new_desktop_session=True
+    aedb, specified_version=AEDT_VERSION, non_graphical=NG_MODE, new_desktop_session=True
 )
 
 # ### Analyze
@@ -202,19 +178,19 @@
 
 # ### Plot impedance
 
-solutions = h3d.post.get_solution_data(expressions='Z(port1,port1)')
+solutions = h3d.post.get_solution_data(expressions="Z(port1,port1)")
 solutions.plot()
 
 # ## Shut Down Electronics Desktop
 
 h3d.release_desktop()
 
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
+# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you
 # can retrieve those project files. The following cell removes all temporary files, including the project folder.
 
 # ## Cleanup
 #
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
+# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you
 # can retrieve those project files. The following cell removes all temporary files, including the project folder.
 
 time.sleep(3)

examples/01-HFSS3DLayout/02_dc_ir_analysis.py

@@ -6,7 +6,7 @@
 #     - Assign SPICE model to components
 #     - Create pin groups
 #     - Create voltage and current sources
-#     - Create SIwave DC anaylsis
+#     - Create SIwave DC analysis
 #     - Create cutout
 # - Import EDB into HFSS 3D Layout
 #     - Analyze
@@ -16,14 +16,17 @@
 # # Preparation
 # Import required packages
 
+import json
+
 # +
 import os
-import json
 import tempfile
 import time
-from pyedb import Edb
+
 from pyaedt import Hfss3dLayout
 from pyaedt.downloads import download_file
+from pyedb import Edb
+
 try:
     from ansys.pyaedt.examples.constants import AEDT_VERSION
 except:
@@ -36,12 +39,8 @@
 
 # Download example board.
 
-aedb = download_file(
-    source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name
-)
-download_file(
-    source="spice", name="ferrite_bead_BLM15BX750SZ1.mod", destination=temp_folder.name
-)
+aedb = download_file(source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name)
+download_file(source="spice", name="ferrite_bead_BLM15BX750SZ1.mod", destination=temp_folder.name)
 
 # # Create a configuration file
 # In this example, we are going to use a configure file to set up layout for analysis.
@@ -53,18 +52,14 @@
 
 cfg["general"] = {
     "s_parameter_library": os.path.join(temp_folder.name, "touchstone"),
-    "spice_model_library": os.path.join(temp_folder.name, "spice")
+    "spice_model_library": os.path.join(temp_folder.name, "spice"),
 }
 
 # ## Change via hole size and plating thickness
 
 cfg["padstacks"] = {
     "definitions": [
-        {
-            "name": "v40h15-3",
-            "hole_diameter": "0.2mm",
-            "hole_plating_thickness": "25um"
-        }
+        {"name": "v40h15-3", "hole_diameter": "0.2mm", "hole_plating_thickness": "25um"}
     ],
 }
 
@@ -78,7 +73,7 @@
         "sub_circuit_name": "BLM15BX750SZ1",
         "apply_to_all": True,  # If True, SPICE model is to be assigned to all components share the same part name.
         # If False, only assign SPICE model to components in "components".
-        "components": []
+        "components": [],
     }
 ]
 
@@ -91,38 +86,24 @@
         "reference_designator": "U4",
         "type": "voltage",
         "magnitude": 5,
-        "positive_terminal": {
-            "net": "5V"
-        },
-        "negative_terminal": {
-            "net": "GND"
-        }
+        "positive_terminal": {"net": "5V"},
+        "negative_terminal": {"net": "GND"},
     }
 ]
 
 # ## Create Current Sources
 # Create current sources between net and pin group.
 
-cfg["pin_groups"] = [
-    {
-        "name": "J5_GND",
-        "reference_designator": "J5",
-        "net": "GND"
-    }
-]
+cfg["pin_groups"] = [{"name": "J5_GND", "reference_designator": "J5", "net": "GND"}]
 
 cfg["sources"].append(
     {
         "name": "J5_VCCR",
         "reference_designator": "J5",
         "type": "current",
         "magnitude": 0.5,
-        "positive_terminal": {
-            "net": "SFPA_VCCR"
-        },
-        "negative_terminal": {
-            "pin_group": "J5_GND"  # Defined in "pin_groups" section.
-        }
+        "positive_terminal": {"net": "SFPA_VCCR"},
+        "negative_terminal": {"pin_group": "J5_GND"},  # Defined in "pin_groups" section.
     }
 )
 cfg["sources"].append(
@@ -131,24 +112,14 @@
         "reference_designator": "J5",
         "type": "current",
         "magnitude": 0.5,
-        "positive_terminal": {
-            "net": "SFPA_VCCT"
-        },
-        "negative_terminal": {
-            "pin_group": "J5_GND"  # Defined in "pin_groups" section.
-        }
+        "positive_terminal": {"net": "SFPA_VCCT"},
+        "negative_terminal": {"pin_group": "J5_GND"},  # Defined in "pin_groups" section.
     }
 )
 
 # ## Create SIwave DC analysis
 
-cfg["setups"] = [
-    {
-        "name": "siwave_dc",
-        "type": "siwave_dc",
-        "dc_slider_position": 0
-    }
-]
+cfg["setups"] = [{"name": "siwave_dc", "type": "siwave_dc", "dc_slider_position": 0}]
 
 # ## Do cutout
 
@@ -176,7 +147,7 @@
         "maximum_iterations": 10,
         "preserve_components_with_model": False,
         "simple_pad_check": True,
-        "keep_lines_as_path": False
+        "keep_lines_as_path": False,
     }
 }
 
@@ -208,10 +179,7 @@
 # ## Load edb into 3D Layout.
 
 siw = Hfss3dLayout(
-    aedb,
-    specified_version=AEDT_VERSION,
-    non_graphical=NG_MODE,
-    new_desktop_session=True
+    aedb, specified_version=AEDT_VERSION, non_graphical=NG_MODE, new_desktop_session=True
 )
 
 # ## Analyze
@@ -228,7 +196,7 @@
 
 # ## Cleanup
 #
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
+# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you
 # can retrieve those project files. The following cell removes all temporary files, including the project folder.
 
 time.sleep(3)

examples/01-HFSS3DLayout/03_gui_manipulation.py

@@ -5,11 +5,14 @@
 # # Preparation
 # Import required packages
 
+import tempfile
+
 # +
 import time
-import tempfile
+
 from pyaedt import Hfss3dLayout
 from pyaedt.downloads import download_file
+
 try:
     from ansys.pyaedt.examples.constants import AEDT_VERSION
 except:
@@ -24,9 +27,7 @@
 
 # Download example board.
 
-aedb = download_file(
-    source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name
-)
+aedb = download_file(source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name)
 
 # ## Launch HFSS 3D Layout
 #
@@ -77,7 +78,7 @@
 
 # ## Cleanup
 #
-# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you 
+# All project files are saved in the folder ``temp_file.dir``. If you've run this example as a Jupyter notbook you
 # can retrieve those project files. The following cell removes all temporary files, including the project folder.
 
 time.sleep(3)