From 82d1d0fc31367cc6f001941bc90c40be872cdb92 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sun, 12 Jan 2025 00:15:07 +0000
Subject: [PATCH] Update revisions Cores-VeeR-EL2 75b13aaa5 Merge pull request
 #339 from chipsalliance/custom-result-merger-full f7ffbe0e0 Merge pull
 request #340 from chipsalliance/test-config 6a7eabe90 block: wait for license
 16c769f89 Makefile: Verilator: ignore LATCH warinign 457ef13c9 tests:
 explicitely set fpga_optimize for rvdv and regression tests 9218ff0f5 Merge
 pull request #332 from chipsalliance/wsip/pmp_test 6388d9711 CI: add custom
 merged coverage report job 09c38f9ed Update inline filter 8cb914e8a add
 pmp_random test 76bbb6db8 pmp test: add useful masks for registers afff8e34f
 increase max cycles in pmp test e5a7dbc90 tools/Makefile: allow providing
 extra args for verilator 9976bbb46 tb: use MAX_CYCLES as parameter to the
 module e29088665 CI: custom regressions: use correct scripts 1c35d3830 CI:
 add custom regression tests for wayback 0

---
 deps.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps.json b/deps.json
index 1b3eeff..6550b64 100644
--- a/deps.json
+++ b/deps.json
@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "5da1679f360b00ae330aab33cc8d79d73dfabb98"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "eb98bbecdec1521dc74d9ace81dcd29c18ef8610"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "6bff4e40b7592b405388ffc9b0a7f0fab948a218"}]}
\ No newline at end of file
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "5da1679f360b00ae330aab33cc8d79d73dfabb98"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "75b13aaa531bf81f81b1f877e05616feb67a42da"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "6bff4e40b7592b405388ffc9b0a7f0fab948a218"}]}
\ No newline at end of file