Binary compatibility with synchronous architectures (e.g x86) using async design

[hatonthecat]

Hi, I've been reading about this project for weeks and have been wondering ways I might want to develop with this software. I've been interested in a node shrink of a 386 or 486 processor (22-130nm), and back when they were on the market in the early 90s, there were a lot of clones. I was curious how asynchronous circuits differ from out-of-order pipelines, and whether they are orthogonal. If an asynchronous circuit that has binary compatibility with a 386 could be demonstrated, it would be interesting to use Efabless' Caravel platform at Skywater, which has 500 1K tiles. The 386 was 275,000 transistors, thus it might be enough to fit.

[nbingham1]

To specifically answer your question: out of order pipelines and asynchronous circuits are orthogonal things. You can build out of order pipelines using asynchronous circuits just like you can build them using synchronous circuits.

However, I think the question you are really asking is about using the tool to build a 386 or 486 processor. This tooling is under active development and targets a very specific design methodology that people historically haven't been able to achieve at scale in an economically viable way. There are three things that need to be completed before a single person could produce a chip with this design methodology and tooling: 1. Modules 2. Cell Placement 3. Routing. These three things would let an expert in the field write large asynchronous systems using production rules and generate a mask for Skywater's 130nm technology. If you have a team of people and a lot of time, you can manually handle the missing design steps. I am actively working on Cell Placement. These are the reasons the releases are all labeled as "pre-release". Currently, it can solve specific needs for small circuits, and it is on the brink of being able to achieve some amount of scale.

Once those three steps are done, the next step would be to finish out the steps required to make HSE and higher level languages viable. This includes State Variable Insertion, Handshake Reshuffling, and Process Decomposition.

I agree that it would be interesting to get a prototype out to Efabless' Caravel platform. We'll probably start with a Tiny Tapeout and a simple clock-domain crossing just to verify the layout systems. Then we'll move up from there.