riscv.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
    <FileList>
        <File path="src/bram.sv" type="file.verilog" enable="1"/>
        <File path="src/cache.sv" type="file.verilog" enable="1"/>
        <File path="src/configuration.sv" type="file.verilog" enable="1"/>
        <File path="src/core.sv" type="file.verilog" enable="1"/>
        <File path="src/ip/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
        <File path="src/ip/regymm/sd_controller.v" type="file.verilog" enable="1"/>
        <File path="src/ip/sdram_controller_hs/sdram_controller_hs.v" type="file.verilog" enable="1"/>
        <File path="src/ramio.sv" type="file.verilog" enable="1"/>
        <File path="src/registers.sv" type="file.verilog" enable="1"/>
        <File path="src/sdcard.sv" type="file.verilog" enable="1"/>
        <File path="src/top.sv" type="file.verilog" enable="1"/>
        <File path="src/uartrx.sv" type="file.verilog" enable="1"/>
        <File path="src/uarttx.sv" type="file.verilog" enable="1"/>
        <File path="tangnano20k.cst" type="file.cst" enable="1"/>
        <File path="tangnano20k.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>