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bfin-dis.cpp
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/*
IDA Pro Processor Module for Blackfin Instruction Set
Copyright (C) 2011
Andreas Schuler <andreas@schulerdev.de>
Based on parts of libopcodes (Free Software Foundation, Inc.) and
Simple Python Byte Code Module (Chris Eagle <cseagle@gmail.com>)
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "bfin.h"
typedef long TIword;
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
#include "dis-asm.h"
static char comment = 0;
static char parallel = 0;
typedef enum
{
c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
} const_forms_t;
const struct formats
{
char *name;
int nbits;
char reloc;
char issigned;
char pcrel;
char scale;
char offset;
char negative;
char positive;
char decimal;
char leading;
char exact;
};
static formats constant_formats[] =
{
{ "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
{ "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
{ "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
{ "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
{ "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
{ "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
{ "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
{ "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
{ "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
{ "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
{ "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
{ "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
{ "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
{ "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
{ "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}
};
bfd_vma bfd_getl16 (const void *p)
{
const bfd_byte *addr = (const bfd_byte *) p;
return (addr[1] << 8) | addr[0];
}
static const char *fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
{
static char buf[60];
if (constant_formats[cf].reloc)
{
bfd_vma ea=(((constant_formats[cf].pcrel?SIGNEXTEND(x,constant_formats[cf].nbits):x) +
constant_formats[cf].offset)<<constant_formats[cf].scale);
if (constant_formats[cf].pcrel)
ea+=pc;
/* truncate to 32-bits for proper symbol lookup/matching */
ea = (bu32)ea;
if (/*outf->symbol_at_address_func (ea, outf) ||*/ !constant_formats[cf].exact)
{
//outf->print_address_func (ea, outf);
qstring name;
if(get_colored_long_name(&name, ea) && !name.empty())
qsnprintf (buf, 60,"%s", name.c_str());
else
qsnprintf (buf, 60,COLSTR("0x%lx",SCOLOR_NUMBER), ea);
return buf;
}
else
{
qsnprintf (buf, 60,COLSTR("0x%lx",SCOLOR_NUMBER), (unsigned long) x);
return buf;
}
}
/* Negative constants have an implied sign bit. */
if (constant_formats[cf].negative)
{
int nb = constant_formats[cf].nbits + 1;
x = x | (1 << constant_formats[cf].nbits);
x = SIGNEXTEND (x, nb);
}
else
x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
if (constant_formats[cf].offset)
x += constant_formats[cf].offset;
if (constant_formats[cf].scale)
x <<= constant_formats[cf].scale;
if (constant_formats[cf].decimal)
{
if (constant_formats[cf].leading)
{
char ps[10];
qsnprintf (ps, 10,COLSTR("%%%ii",SCOLOR_NUMBER), constant_formats[cf].leading);
qsnprintf (buf, 60,ps, x);
}
else
{
qsnprintf (buf, 60,COLSTR("%li",SCOLOR_NUMBER), x);
}
}
else
{
if (constant_formats[cf].issigned && x < 0)
qsnprintf (buf, 60,COLSTR("-0x%x",SCOLOR_NUMBER), abs (x));
else
qsnprintf (buf, 60,COLSTR("0x%lx",SCOLOR_NUMBER), (unsigned long) x);
}
return buf;
}
static bu32 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
{
if (0 && constant_formats[cf].reloc)
{
bu32 ea = (((constant_formats[cf].pcrel
? SIGNEXTEND (x, constant_formats[cf].nbits)
: x) + constant_formats[cf].offset)
<< constant_formats[cf].scale);
if (constant_formats[cf].pcrel)
ea += pc;
return ea;
}
/* Negative constants have an implied sign bit. */
if (constant_formats[cf].negative)
{
int nb = constant_formats[cf].nbits + 1;
x = x | (1 << constant_formats[cf].nbits);
x = SIGNEXTEND (x, nb);
}
else if (constant_formats[cf].issigned)
x = SIGNEXTEND (x, constant_formats[cf].nbits);
x += constant_formats[cf].offset;
x <<= constant_formats[cf].scale;
return x;
}
enum machine_registers
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
REG_L2, REG_L3,
REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
REG_AQ, REG_V, REG_VS,
REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
REG_LASTREG,
};
enum reg_class
{
rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
rc_sysregs3, rc_allregs,
LIM_REG_CLASSES
};
static const char * const reg_names[] =
{
"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
"R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
"P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
"A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
"M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
"L2", "L3",
"AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
"AQ", "V", "VS",
"sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
"LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
"CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
"RETE", "EMUDAT",
"R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
"P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
"P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
"I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
"B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
"I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
"B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
"AC0_COPY", "V_COPY", "RND_MOD",
"LASTREG",
0
};
char *REGNAME(unsigned char x)
{
static char out[20];
if(x<REG_LASTREG)
qsnprintf(out,20,COLSTR("%s",SCOLOR_REG),reg_names[x]);
else
{
qsnprintf(out,20,COLSTR(".. Illegal register ..",SCOLOR_REG));
}
return out;
}
/* RL(0..7). */
static const enum machine_registers decode_dregs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
};
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
/* RH(0..7). */
static const enum machine_registers decode_dregs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
};
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
/* R(0..7). */
static const enum machine_registers decode_dregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
};
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
/* R BYTE(0..7). */
static const enum machine_registers decode_dregs_byte[] =
{
REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
};
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
/* P(0..5) SP FP. */
static const enum machine_registers decode_pregs[] =
{
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define pregs(x) REGNAME (decode_pregs[(x) & 7])
#define spfp(x) REGNAME (decode_spfp[(x) & 1])
#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
#define accum(x) REGNAME (decode_accum[(x) & 1])
/* I(0..3). */
static const enum machine_registers decode_iregs[] =
{
REG_I0, REG_I1, REG_I2, REG_I3,
};
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
/* M(0..3). */
static const enum machine_registers decode_mregs[] =
{
REG_M0, REG_M1, REG_M2, REG_M3,
};
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
/* dregs pregs. */
static const enum machine_registers decode_dpregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
/* [dregs pregs]. */
static const enum machine_registers decode_gregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs)]. */
static const enum machine_registers decode_regs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
};
#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
static const enum machine_registers decode_regs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
};
#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
static const enum machine_registers decode_regs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
};
#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
static const enum machine_registers decode_statbits[] =
{
REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
};
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
/* LC0 LC1. */
static const enum machine_registers decode_counters[] =
{
REG_LC0, REG_LC1,
};
#define counters(x) REGNAME (decode_counters[(x) & 1])
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
/* [dregs pregs (iregs mregs) (bregs lregs)
dregs2_sysregs1 open sysregs2 sysregs3]. */
static const enum machine_registers decode_allregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
REG_LASTREG,
};
#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
#define IS_SYSREG(g,r) (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
#define IS_RESERVEDREG(g,r) (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
#define allreg(r,g) (!IS_RESERVEDREG (g, r))
#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
#define imm16(x) fmtconst (c_imm16, x, 0, outf)
#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
#define imm3(x) fmtconst (c_imm3, x, 0, outf)
#define imm4(x) fmtconst (c_imm4, x, 0, outf)
#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
#define imm5(x) fmtconst (c_imm5, x, 0, outf)
#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
#define imm6(x) fmtconst (c_imm6, x, 0, outf)
#define imm7(x) fmtconst (c_imm7, x, 0, outf)
#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
#define imm8(x) fmtconst (c_imm8, x, 0, outf)
#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
#define imm32(x) fmtconst (c_imm32, x, 0, outf)
#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
/* (arch.pm)arch_disassembler_functions. */
#ifndef OUTS
#define OUTS(p, txt) qstrncat((p)->str,txt,MAXSTR)
#endif
#ifndef OUTC
#define OUTC(p, txt) qstrncat((p)->comment,txt,MAXSTR)
#endif
static void amod0 (int s0, int x0, disassemble_info *outf)
{
if (s0 == 1 && x0 == 0)
OUTS (outf, " (S)");
else if (s0 == 0 && x0 == 1)
OUTS (outf, " (CO)");
else if (s0 == 1 && x0 == 1)
OUTS (outf, " (SCO)");
}
static void amod1 (int s0, int x0, disassemble_info *outf)
{
if (s0 == 0 && x0 == 0)
OUTS (outf, " (NS)");
else if (s0 == 1 && x0 == 0)
OUTS (outf, " (S)");
}
static void amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
{
if (s0 == 1 && x0 == 0 && aop0 == 0)
OUTS (outf, " (S)");
else if (s0 == 0 && x0 == 1 && aop0 == 0)
OUTS (outf, " (CO)");
else if (s0 == 1 && x0 == 1 && aop0 == 0)
OUTS (outf, " (SCO)");
else if (s0 == 0 && x0 == 0 && aop0 == 2)
OUTS (outf, " (ASR)");
else if (s0 == 1 && x0 == 0 && aop0 == 2)
OUTS (outf, " (S, ASR)");
else if (s0 == 0 && x0 == 1 && aop0 == 2)
OUTS (outf, " (CO, ASR)");
else if (s0 == 1 && x0 == 1 && aop0 == 2)
OUTS (outf, " (SCO, ASR)");
else if (s0 == 0 && x0 == 0 && aop0 == 3)
OUTS (outf, " (ASL)");
else if (s0 == 1 && x0 == 0 && aop0 == 3)
OUTS (outf, " (S, ASL)");
else if (s0 == 0 && x0 == 1 && aop0 == 3)
OUTS (outf, " (CO, ASL)");
else if (s0 == 1 && x0 == 1 && aop0 == 3)
OUTS (outf, " (SCO, ASL)");
}
static void searchmod (int r0, disassemble_info *outf)
{
if (r0 == 0)
OUTS (outf, "GT");
else if (r0 == 1)
OUTS (outf, "GE");
else if (r0 == 2)
OUTS (outf, "LT");
else if (r0 == 3)
OUTS (outf, "LE");
}
static void aligndir (int r0, disassemble_info *outf)
{
if (r0 == 1)
OUTS (outf, " (R)");
}
static int decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *s0, *s1;
if (h0)
s0 = dregs_hi (src0);
else
s0 = dregs_lo (src0);
if (h1)
s1 = dregs_hi (src1);
else
s1 = dregs_lo (src1);
OUTS (outf, s0);
OUTS (outf, " * ");
OUTS (outf, s1);
return 0;
}
static int decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *a;
const char *sop = "<unknown op>";
if (which)
a = COLSTR("A1",SCOLOR_REG);
else
a = COLSTR("A0",SCOLOR_REG);
if (op == 3)
{
OUTS (outf, a);
return 0;
}
switch (op)
{
case 0: sop = " = "; break;
case 1: sop = " += "; break;
case 2: sop = " -= "; break;
default: break;
}
OUTS (outf, a);
OUTS (outf, sop);
decode_multfunc (h0, h1, src0, src1, outf);
return 0;
}
static void decode_optmode (int mod, int MM, disassemble_info *outf)
{
if (mod == 0 && MM == 0)
return;
OUTS (outf, " (");
if (MM && !mod)
{
OUTS (outf, "M)");
return;
}
if (MM)
OUTS (outf, "M, ");
if (mod == M_S2RND)
OUTS (outf, "S2RND");
else if (mod == M_T)
OUTS (outf, "T");
else if (mod == M_W32)
OUTS (outf, "W32");
else if (mod == M_FU)
OUTS (outf, "FU");
else if (mod == M_TFU)
OUTS (outf, "TFU");
else if (mod == M_IS)
OUTS (outf, "IS");
else if (mod == M_ISS2)
OUTS (outf, "ISS2");
else if (mod == M_IH)
OUTS (outf, "IH");
else if (mod == M_IU)
OUTS (outf, "IU");
else
abort ();
OUTS (outf, ")");
}
#define DREG(x) (outf->saved_state.dpregs[x])
#define GREG(x, i) DPREG ((x) | ((i) << 3))
#define DPREG(x) (outf->saved_state.dpregs[x])
#define DREG(x) (outf->saved_state.dpregs[x])
#define PREG(x) (outf->saved_state.dpregs[(x) + 8])
#define SPREG PREG (6)
#define FPREG PREG (7)
#define IREG(x) (outf->saved_state.iregs[x])
#define MREG(x) (outf->saved_state.mregs[x])
#define BREG(x) (outf->saved_state.bregs[x])
#define LREG(x) (outf->saved_state.lregs[x])
#define AXREG(x) (outf->saved_state.ax[x])
#define AWREG(x) (outf->saved_state.aw[x])
#define LCREG(x) (outf->saved_state.lc[x])
#define LTREG(x) (outf->saved_state.lt[x])
#define LBREG(x) (outf->saved_state.lb[x])
#define RETSREG (outf->saved_state.rets)
static bu32 *get_allreg (int grp, int reg, disassemble_info *outf)
{
int fullreg = (grp << 3) | reg;
/* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
, , , , , , , ,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
REG_CYCLES2,
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
REG_LASTREG */
switch (fullreg >> 2)
{
case 0: case 1: return &DREG (reg);
case 2: case 3: return &PREG (reg);
case 4: return &IREG (reg & 3);
case 5: return &MREG (reg & 3);
case 6: return &BREG (reg & 3);
case 7: return &LREG (reg & 3);
default:
switch (fullreg)
{
case 32: return &AXREG (0);
case 33: return &AWREG (0);
case 34: return &AXREG (1);
case 35: return &AWREG (1);
case 39: return &RETSREG;
case 48: return &LCREG (0);
case 49: return <REG (0);
case 50: return &LBREG (0);
case 51: return &LCREG (1);
case 52: return <REG (1);
case 53: return &LBREG (1);
}
}
abort ();
}
void add_preg_dataref_l(bu32 val, disassemble_info *outf)
{
SET_DATAREF(outf,val,dr_U,DMODE_LOAD_LOW);
}
void add_preg_dataref_h(bu32 val, disassemble_info *outf)
{
SET_DATAREF(outf,val,dr_U,DMODE_LOAD_HIGH);
}
void add_preg_dataref_r(int ptr, disassemble_info *outf)
{
if(ptr<6)
SET_DATAREF(outf,ptr/**get_allreg (1, ptr, outf)*/,dr_R,DMODE_READPTR);
}
void add_preg_dataref_w(int ptr, disassemble_info *outf)
{
if(ptr<6)
SET_DATAREF(outf,ptr/**get_allreg (1, ptr, outf)*/,dr_W,DMODE_WRITEPTR);
}
static int decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
{
/* ProgCtrl
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
if (prgfunc == 0 && poprnd == 0)
OUTS (outf, "NOP");
else if (parallel)
return 0;
else if (prgfunc == 1 && poprnd == 0)
{
OUTS (outf, "RTS");
SET_FEATURE(outf,CF_STOP);
}
else if (prgfunc == 1 && poprnd == 1)
{
OUTS (outf, "RTI");
SET_FEATURE(outf,CF_STOP);
}
else if (prgfunc == 1 && poprnd == 2)
{
OUTS (outf, "RTX");
SET_FEATURE(outf,CF_STOP);
}
else if (prgfunc == 1 && poprnd == 3)
{
OUTS (outf, "RTN");
SET_FEATURE(outf,CF_STOP);
}
else if (prgfunc == 1 && poprnd == 4)
{
OUTS (outf, "RTE");
SET_FEATURE(outf,CF_STOP);
}
else if (prgfunc == 2 && poprnd == 0)
OUTS (outf, "IDLE");
else if (prgfunc == 2 && poprnd == 3)
OUTS (outf, "CSYNC");
else if (prgfunc == 2 && poprnd == 4)
OUTS (outf, "SSYNC");
else if (prgfunc == 2 && poprnd == 5)
OUTS (outf, "EMUEXCPT");
else if (prgfunc == 3 && IS_DREG (0, poprnd))
{
OUTS (outf, "CLI ");
OUTS (outf, dregs (poprnd));
}
else if (prgfunc == 4 && IS_DREG (0, poprnd))
{
OUTS (outf, "STI ");
OUTS (outf, dregs (poprnd));
}
else if (prgfunc == 5 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
SET_FEATURE(outf,CF_STOP/*|CF_JUMP*/);
outf->itype=i_jump;
}
else if (prgfunc == 6 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
//SET_FEATURE(outf,CF_JUMP|CF_CALL);
outf->itype=i_call;
}
else if (prgfunc == 7 && IS_PREG (1, poprnd))
{
OUTS (outf, "CALL (PC + ");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
//SET_FEATURE(outf,CF_JUMP|CF_CALL);
outf->itype=i_call;
}
else if (prgfunc == 8 && IS_PREG (1, poprnd))
{
OUTS (outf, "JUMP (PC + ");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
//SET_FEATURE(outf,CF_STOP|CF_JUMP);
outf->itype=i_jump;
}
else if (prgfunc == 9)
{
OUTS (outf, "RAISE ");
OUTS (outf, uimm4 (poprnd));
}
else if (prgfunc == 10)
{
OUTS (outf, "EXCPT ");
OUTS (outf, uimm4 (poprnd));
}
else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
{
OUTS (outf, "TESTSET (");
OUTS (outf, pregs (poprnd));
OUTS (outf, ")");
}
else
return 0;
return 2;
}
static int decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
{
/* CaCTRL
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
if (parallel)
return 0;
if (a == 0 && op == 0)
{
OUTS (outf, "PREFETCH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 1)
{
OUTS (outf, "FLUSHINV[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 2)
{
OUTS (outf, "FLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 0 && op == 3)
{
OUTS (outf, "IFLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "]");
}
else if (a == 1 && op == 0)
{
OUTS (outf, "PREFETCH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 1)
{
OUTS (outf, "FLUSHINV[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 2)
{
OUTS (outf, "FLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else if (a == 1 && op == 3)
{
OUTS (outf, "IFLUSH[");
OUTS (outf, pregs (reg));
OUTS (outf, "++]");
}
else
return 0;
return 2;
}
static int decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
{
/* PushPopReg
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
if (parallel)
return 0;
if (W == 0 && mostreg (reg, grp))
{
OUTS (outf, allregs (reg, grp));
OUTS (outf, " = [SP++]");
}
else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
{
OUTS (outf, "[--SP] = ");
OUTS (outf, allregs (reg, grp));
}
else
return 0;
return 2;
}
static int decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
{
/* PushPopMultiple
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
if (parallel)
return 0;
if (pr > 5)
return 0;
if (W == 1 && d == 1 && p == 1)
{
OUTS (outf, "[--SP] = (R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ", P5:");
OUTS (outf, imm5d (pr));
OUTS (outf, ")");
}
else if (W == 1 && d == 1 && p == 0 && pr == 0)
{
OUTS (outf, "[--SP] = (R7:");
OUTS (outf, imm5d (dr));
OUTS (outf, ")");
}