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[Feature] Implement Analytical Placement #13
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Hi @Sov-trotter , thank you for your interest! First, I will provide some context for this project. This project is not really targeting ASIC design flows and is more geared towards devices like heterogeneous coarse-grained reconfigurable arrays. Particularly, this was targeting KiloCore and related architectures (I spent some time in this group during graduate school). This project has some really neat features such as the ability to place and route in 3 dimensions, use arbitrary underlying connection topologies, arbitrary processor deletion, custom placement objective functions etc. etc., but it's definitely different from my understanding of what typical ASIC flows might look like. Unfortunately, I ended moving out of this research group before publishing anything on this project and it's basically been in maintenance mode for the last 4 years. I believe that it is used occasionally within the group to place and route various applications, but active development and incorporation into research projects has for all intents and purposes stopped. With that context, unless you had an immediate project or use case in mind for which this package would be useful (to that end, I'd be happy to supply what assistance I can), I sadly don't think that contributing to this project (welcome as it would be) would be an efficient use of your time. Regarding post-placement steps, there is a validation step following placement Mapper2.jl/src/Place/SA/Struct.jl Line 487 in 9c6c131
Please let me know if you have further questions 😄. |
This is one of the rarest packages I came across in context of ASIC design flow within the julia ecosystem :)
I would be happy to contribute and work on this package and one starting point I can think of is Analytical Placement?
Also are there any legalisation steps in place after the SA steps?
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