Question about CHA register

[feilll]

Hi,

I am trying to reproduce your code on my machine, and while working with the record_stat.c kernel module, I encountered variables related to the CHA hardware register. However, after reviewing the Intel IA32 manual, I was unable to find any reference to the CHA hardware register address.

Could you kindly clarify where you obtained the value for this variable or provide some guidance on how to access the CHA register values? Any insights would be greatly appreciated.

Thank you!

[alannair]

I, too, am facing the same conundrum.
Dear authors, please specify the exact registers (and the corresponding CPU model) which you used to measure queue occupancy and request arrival rate.
It would help us a lot.

[webglider]

Hello @feilll and @alannair,

Thank you for the questions!

Colloid implementation programs CHA hardware registers to measure queue occupancy and request arrival rates via the TOR_OCCUPANCY and TOR_INSERTS events. These registers/events are documented in the Intel "uncore performance monitoring manuals" which are available separately for different processor generations. The aforementioned CHA counters are available on recent generations of Intel processors including---Cascade Lake (2nd gen Xeon), Ice Lake (3rd Gen Xeon) and Sapphire Rapids (4th Gen Xeon). I also believe they are available on some of the older generations such as Haswell.

The current Colloid latency measurement code in the repository assumes Intel Icelake processors (3rd gen Xeon). I also have a port for Cascade Lake (2nd gen Xeon) which I am happy to provide. While I don't have access to other generation servers, I am happy to provide as much help as possible in porting the implementation. Which architecture / processor generation are you using?

For reference, in the current implementation, the CHA register base addresses (i.e., the constants specified here) were determined using Table 1-9 on page 31 of the Intel Icelake uncore manual (https://cdrdv2-public.intel.com/679093/639778%20ICX%20UPG%20v1.pdf).

Feel free to keep the questions coming. Also, happy to hop on a call and discuss if that is easier. You can always reach me via my email: midhul@cs.cornell.edu

[alannair]

Thank you so much for this detailed answer!

[jhk16]

Hi,

I am also trying to reproduce your paper's results (especially TPP with colloid), but my system is Cascade Lake (2nd gen Xeon). So, when I load the colloid-mon.c kernel module, it gets stuck with a kernel bug because it has no hardware event counters. (I guess)

Since you mentioned you also have a colloid ported version for Cascade Lake, I'm wondering if you have a plan to open the colloid implementation for Cascade Lake.

Thanks in advance for your attention.

[webglider]

Hi @jhk16,

Thanks for the interest! Yes, definitely. I will push the Cascade lake port within the next 48 hours, and let you know.

[jhk16]

Thanks for the quick reply! Looking forward to the update.

[webglider]

@jhk16 Pushed updates with Cascadelake support for TPP+Colloid. Please see the updated documentation in tpp/README.md. In particular, you can use the clx-native backend for Cascadelake support.

[jhk16]

@webglider Thank you!