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phy: sx127x: Increase test coverage also for half-megahertz values
1 parent 717c6a3 commit 969ee24

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2 files changed

+13
-6
lines changed

2 files changed

+13
-6
lines changed

lora-phy/src/sx127x/mod.rs

+12-6
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,9 @@ const SCALE: u32 = 8;
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const STEP_SCALED: u32 = 32_000_000 >> (19 - SCALE);
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fn freq_to_pll_step(freq_in_hz: u32) -> u32 {
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// NB! This works well at full MHz level, though there
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// are small differences when delving into 0.1MHz level
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// We can use simplified integer formula which gives the same
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// value for whole and half Mhz values ((i.e. 868.0, 868.5, 869, ...)
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// `(freq_in_hz as f64 / 61.03515625) as u32`
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(freq_in_hz / STEP_SCALED) << SCALE
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}
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@@ -556,12 +557,17 @@ where
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mod tests {
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use super::*;
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// FXOSC[32 MHz] * 1000000 (Hz/MHz) / 524288 (2^19)
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const FREQUENCY_SYNTHESIZER_STEP: f64 = 61.03515625;
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#[test]
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fn pll_step_freq_u32_vs_f64() {
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// Test whether our frequency -> pll_step and vice versa are good enough
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const FREQUENCY_SYNTHESIZER_STEP: f64 = 61.03515625;
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for freq in 137..=1020 {
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let f = freq * 1_000_000;
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// Simplified integer calculation converges with floating
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// point formula for full and half megahertz values
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const D: u32 = 2;
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for freq in D * 137..=(D * 1020) {
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let f = freq * (1_000_000 / D);
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let pll = freq_to_pll_step(f);
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assert_eq!(pll, (f as f64 / FREQUENCY_SYNTHESIZER_STEP) as u32);
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assert_eq!(pll_step_to_freq(pll), f);

lora-phy/src/sx127x/sx1276.rs

+1
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,7 @@ impl Sx127xVariant for Sx1276 {
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radio: &mut Sx127x<SPI, IV, Self>,
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) -> Result<i16, RadioError> {
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let frequency_in_hz = {
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// TODO: Keep frequency in radio settings?
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let msb = radio.read_register(Register::RegFrfMsb).await? as u32;
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let mid = radio.read_register(Register::RegFrfMid).await? as u32;
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let lsb = radio.read_register(Register::RegFrfLsb).await? as u32;

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