ModuleCode Timer 1 ISR triggering significantly more frequently than required

[AreasAside]

The timer 1 overflow interrupt is used to update the PID controller. A separate counter inside the interrupt is then used to control the timing of the PID. We could eliminate the extra timer and eliminate the unnecessary overhead that the ISR creates by utilizing the compare match interrupt instead of the overflow. As an added bonus we would have much finer control over the PID loop time.

Was there a reason that the overflow interrupt was used instead of the compare match interrupt?
Is it desirable to maintain ~16.4ms update time for the PID or can we pick a rounder value?
Anything else I'm missing?

Before:

13:44:39.648 -> 3033: Timer interrupts per second: 491
13:44:39.695 -> 3033: PID ticks per second: 61
13:44:42.648 -> 6034: Timer interrupts per second: 490
13:44:42.694 -> 6034: PID ticks per second: 61
13:44:45.648 -> 9035: Timer interrupts per second: 490
13:44:45.648 -> 9035: PID ticks per second: 61

After:

15:00:03.018 -> 3032: Timer interrupts per second: 50
15:00:03.065 -> 3032: PID ticks per second: 50
15:00:06.018 -> 6032: Timer interrupts per second: 50
15:00:06.065 -> 6032: PID ticks per second: 50
15:00:09.018 -> 9032: Timer interrupts per second: 50
15:00:09.065 -> 9032: PID ticks per second: 50