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Main.syr
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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: Main.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Main.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Main"
Output Format : NGC
Target Device : xc3s50a-4-tq144
---- Source Options
Top Module Name : Main
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "Main.v" in library work
Module <Main> compiled
No errors in compilation
Analysis of file <"Main.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <Main> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <Main>.
Module <Main> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Main>.
Related source file is "Main.v".
WARNING:Xst:1781 - Signal <sine> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <halfsine> is used but never assigned. Tied to default value.
WARNING:Xst:1781 - Signal <fsine> is used but never assigned. Tied to default value.
Register <dac_c2> equivalent to <dac_c1> has been removed
Found 32x30-bit ROM for signal <address$rom0000>.
Found 4-bit register for signal <LED>.
Found 10-bit register for signal <dac_c1>.
Found 5-bit up counter for signal <address>.
Summary:
inferred 1 ROM(s).
inferred 1 Counter(s).
inferred 14 D-type flip-flop(s).
Unit <Main> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
32x30-bit ROM : 1
# Counters : 1
5-bit up counter : 1
# Registers : 2
10-bit register : 1
4-bit register : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 1
32x30-bit ROM : 1
# Counters : 1
5-bit up counter : 1
# Registers : 14
Flip-Flops : 14
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <Main> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Main, actual ratio is 8.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 19
Flip-Flops : 19
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : Main.ngr
Top Level Output File Name : Main
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 34
Cell Usage :
# BELS : 97
# INV : 3
# LUT2 : 3
# LUT2_L : 2
# LUT3 : 8
# LUT3_D : 1
# LUT3_L : 1
# LUT4 : 57
# LUT4_L : 15
# MUXF5 : 7
# FlipFlops/Latches : 19
# FDC : 5
# FDC_1 : 10
# FDE_1 : 4
# Clock Buffers : 1
# BUFG : 1
# IO Buffers : 34
# IBUF : 6
# OBUF : 28
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50atq144-4
Number of Slices: 46 out of 704 6%
Number of Slice Flip Flops: 15 out of 1408 1%
Number of 4 input LUTs: 90 out of 1408 6%
Number of IOs: 34
Number of bonded IOBs: 34 out of 108 31%
IOB Flip Flops: 4
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | IBUF+BUFG | 19 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst_n_inv(rst_n_inv1_INV_0:O) | NONE(address_0) | 15 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 5.780ns (Maximum Frequency: 172.996MHz)
Minimum input arrival time before clock: 7.162ns
Maximum output required time after clock: 5.558ns
Maximum combinational path delay: 6.002ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 5.780ns (frequency: 172.996MHz)
Total number of paths / destination ports: 225 / 15
-------------------------------------------------------------------------
Delay: 5.780ns (Levels of Logic = 4)
Source: address_4 (FF)
Destination: dac_c1_8 (FF)
Source Clock: clk falling
Destination Clock: clk falling
Data Path: address_4 to dac_c1_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 36 0.591 1.343 address_4 (address_4)
LUT4:I1->O 1 0.643 0.452 dac_c1_mux0000<8>43_SW1 (N9)
LUT4_L:I2->LO 1 0.648 0.132 dac_c1_mux0000<8>43 (dac_c1_mux0000<8>43)
LUT3:I2->O 1 0.648 0.423 dac_c1_mux0000<8>78 (dac_c1_mux0000<8>78)
LUT4:I3->O 1 0.648 0.000 dac_c1_mux0000<8>251 (dac_c1_mux0000<8>)
FDC_1:D 0.252 dac_c1_8
----------------------------------------
Total 5.780ns (3.430ns logic, 2.350ns route)
(59.3% logic, 40.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 174 / 18
-------------------------------------------------------------------------
Offset: 7.162ns (Levels of Logic = 6)
Source: sel_n<0> (PAD)
Destination: dac_c1_8 (FF)
Destination Clock: clk falling
Data Path: sel_n<0> to dac_c1_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 9 0.849 0.963 sel_n_0_IBUF (sel_n_0_IBUF)
LUT3:I0->O 7 0.648 0.851 dac_c1_cmp_eq00021 (dac_c1_cmp_eq0002)
LUT4:I0->O 1 0.648 0.452 dac_c1_mux0000<8>43_SW1 (N9)
LUT4_L:I2->LO 1 0.648 0.132 dac_c1_mux0000<8>43 (dac_c1_mux0000<8>43)
LUT3:I2->O 1 0.648 0.423 dac_c1_mux0000<8>78 (dac_c1_mux0000<8>78)
LUT4:I3->O 1 0.648 0.000 dac_c1_mux0000<8>251 (dac_c1_mux0000<8>)
FDC_1:D 0.252 dac_c1_8
----------------------------------------
Total 7.162ns (4.341ns logic, 2.821ns route)
(60.6% logic, 39.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 24 / 24
-------------------------------------------------------------------------
Offset: 5.558ns (Levels of Logic = 1)
Source: dac_c1_9 (FF)
Destination: dac_c1<9> (PAD)
Source Clock: clk falling
Data Path: dac_c1_9 to dac_c1<9>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 2 0.591 0.447 dac_c1_9 (dac_c1_9)
OBUF:I->O 4.520 dac_c1_9_OBUF (dac_c1<9>)
----------------------------------------
Total 5.558ns (5.111ns logic, 0.447ns route)
(92.0% logic, 8.0% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Delay: 6.002ns (Levels of Logic = 2)
Source: clk (PAD)
Destination: dac_wrt1 (PAD)
Data Path: clk to dac_wrt1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.849 0.633 clk_IBUF (dac_clk2_OBUF1)
OBUF:I->O 4.520 dac_wrt1_OBUF (dac_wrt1)
----------------------------------------
Total 6.002ns (5.369ns logic, 0.633ns route)
(89.5% logic, 10.5% route)
=========================================================================
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.58 secs
-->
Total memory usage is 268996 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)
Number of infos : 0 ( 0 filtered)