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i2s_ns0921.fit.rpt
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Fitter report for i2s_ns0921
Fri Jul 16 09:27:43 2021
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Control Signals
16. Global & Other Fast Signals
17. Routing Usage Summary
18. LAB Logic Elements
19. LAB-wide Signals
20. LAB Signals Sourced
21. LAB Signals Sourced Out
22. LAB Distinct Inputs
23. Fitter Device Options
24. Fitter Messages
25. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Fri Jul 16 09:27:43 2021 ;
; Quartus Prime Version ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
; Revision Name ; i2s_ns0921 ;
; Top-level Entity Name ; i2s_ns0921 ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 97 / 240 ( 40 % ) ;
; Total pins ; 6 / 80 ( 8 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /home/naoki/altera/i2s_ns0921/i2s_ns0921.pin.
+------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
; Total logic elements ; 97 / 240 ( 40 % ) ;
; -- Combinational with no register ; 45 ;
; -- Register only ; 6 ;
; -- Combinational with a register ; 46 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 50 ;
; -- 3 input functions ; 20 ;
; -- 2 input functions ; 18 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 92 ;
; -- arithmetic mode ; 5 ;
; -- qfbk mode ; 1 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 11 ;
; -- asynchronous clear/load mode ; 2 ;
; ; ;
; Total registers ; 52 / 240 ( 22 % ) ;
; Total LABs ; 12 / 24 ( 50 % ) ;
; Logic elements in carry chains ; 6 ;
; Virtual pins ; 0 ;
; I/O pins ; 6 / 80 ( 8 % ) ;
; -- Clock pins ; 1 / 4 ( 25 % ) ;
; ; ;
; Global signals ; 4 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ; ;
; -- Total Fixed Point DSP Blocks ; 0 ;
; -- Total Floating Point DSP Blocks ; 0 ;
; ; ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 8.1% / 9.3% / 6.7% ;
; Peak interconnect usage (total/H/V) ; 8.1% / 9.3% / 6.7% ;
; Maximum fan-out ; 33 ;
; Highest non-global fan-out ; 18 ;
; Total fan-out ; 385 ;
; Average fan-out ; 3.74 ;
+---------------------------------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; mclk_in ; 12 ; 1 ; 1 ; 3 ; 3 ; 14 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; sclk ; 1 ; 2 ; 2 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; bck ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; lrck ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; mclk ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+----------------------------+------------------+------------------------+----------------------+-------+----------------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+----------------------------+------------------+------------------------+----------------------+-------+----------------------------+---------------------+
; sda ; 3 ; 1 ; 1 ; 4 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3V Schmitt Trigger Input ; 16mA ; no ; User ; 10 pF ; I2C_to_GPIO:i2c|sda_out~en ; - ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+----------------------------+------------------+------------------------+----------------------+-------+----------------------------+---------------------+
+-----------------------------------------------------------+
; I/O Bank Usage ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1 ; 5 / 38 ( 13 % ) ; 3.3V ; -- ;
; 2 ; 1 / 42 ( 2 % ) ; 3.3V ; -- ;
+----------+-----------------+---------------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+---------------------------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+---------------------------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; sclk ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 2 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 3 ; 1 ; 1 ; sda ; bidir ; 3.3V Schmitt Trigger Input ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 5 ; 3 ; 1 ; lrck ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 6 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 7 ; 5 ; 1 ; bck ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; mclk_in ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 15 ; 9 ; 1 ; mclk ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 16 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 17 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 18 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 19 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 20 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 21 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 27 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 28 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 29 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 30 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 34 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 35 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 36 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 37 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 38 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 39 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 40 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 41 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 42 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 43 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 44 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 48 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 49 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 50 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 51 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 52 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 53 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 54 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 55 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 56 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 57 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 58 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 62 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 67 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 68 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 69 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 70 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 71 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 72 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 73 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 74 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; 75 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 76 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 77 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 78 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 82 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 83 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 84 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 85 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 86 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 87 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 88 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 89 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 90 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 91 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 92 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 96 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 97 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 98 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 99 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 100 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+----------+------------+----------+---------------------------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; 2.5 V ; 10 pF ; Not Available ;
; 1.8 V ; 10 pF ; Not Available ;
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; |i2s_ns0921 ; 97 (28) ; 52 ; 0 ; 6 ; 0 ; 45 (16) ; 6 (0) ; 46 (12) ; 6 (6) ; 1 (1) ; |i2s_ns0921 ; work ;
; |I2C_to_GPIO:i2c| ; 69 (69) ; 40 ; 0 ; 0 ; 0 ; 29 (29) ; 6 (6) ; 34 (34) ; 0 (0) ; 0 (0) ; |i2s_ns0921|I2C_to_GPIO:i2c ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------+
; Delay Chain Summary ;
+---------+----------+---------------+
; Name ; Pin Type ; Pad to Core 0 ;
+---------+----------+---------------+
; mclk ; Output ; -- ;
; bck ; Output ; -- ;
; lrck ; Output ; -- ;
; sda ; Bidir ; (0) ;
; mclk_in ; Input ; (0) ;
; sclk ; Input ; (0) ;
+---------+----------+---------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-------------------------------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------------------------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; I2C_to_GPIO:i2c|GPIO_input_reg[7]~1 ; LC_X5_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; I2C_to_GPIO:i2c|GPIO_output[0] ; LC_X4_Y1_N8 ; 3 ; Output enable ; no ; -- ; -- ;
; I2C_to_GPIO:i2c|GPIO_output[1] ; LC_X3_Y2_N6 ; 3 ; Output enable ; no ; -- ; -- ;
; I2C_to_GPIO:i2c|count[2]~6 ; LC_X4_Y2_N4 ; 4 ; Clock enable ; no ; -- ; -- ;
; I2C_to_GPIO:i2c|reset ; LC_X5_Y2_N8 ; 3 ; Async. clear ; no ; -- ; -- ;
; I2C_to_GPIO:i2c|sclk ; LC_X2_Y3_N8 ; 33 ; Clock, Clock enable ; yes ; Global Clock ; GCLK3 ;
; I2C_to_GPIO:i2c|sda ; LC_X2_Y2_N0 ; 14 ; Clock ; yes ; Global Clock ; GCLK2 ;
; I2C_to_GPIO:i2c|start_stop ; LC_X5_Y2_N0 ; 13 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; bck_m ; LC_X2_Y3_N6 ; 9 ; Clock ; yes ; Global Clock ; GCLK1 ;
; count_bck_or ; LC_X3_Y3_N4 ; 3 ; Sync. load ; no ; -- ; -- ;
; mclk_in ; PIN_12 ; 14 ; Clock ; yes ; Global Clock ; GCLK0 ;
+-------------------------------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+----------------------+-------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+----------------------+-------------+---------+----------------------+------------------+
; I2C_to_GPIO:i2c|sclk ; LC_X2_Y3_N8 ; 33 ; Global Clock ; GCLK3 ;
; I2C_to_GPIO:i2c|sda ; LC_X2_Y2_N0 ; 14 ; Global Clock ; GCLK2 ;
; bck_m ; LC_X2_Y3_N6 ; 9 ; Global Clock ; GCLK1 ;
; mclk_in ; PIN_12 ; 14 ; Global Clock ; GCLK0 ;
+----------------------+-------------+---------+----------------------+------------------+
+--------------------------------------------+
; Routing Usage Summary ;
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 45 / 784 ( 6 % ) ;
; Direct links ; 49 / 888 ( 6 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 10 / 32 ( 31 % ) ;
; LUT chains ; 10 / 216 ( 5 % ) ;
; Local interconnects ; 128 / 888 ( 14 % ) ;
; R4s ; 51 / 704 ( 7 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.08) ; Number of LABs (Total = 12) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 5 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 12) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 1 ;
; 1 Clock ; 8 ;
; 1 Clock enable ; 1 ;
; 1 Sync. clear ; 2 ;
; 1 Sync. load ; 1 ;
; 2 Clocks ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.17) ; Number of LABs (Total = 12) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 4 ;
; 11 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.42) ; Number of LABs (Total = 12) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 3 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.58) ; Number of LABs (Total = 12) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated with weak pull-up ;
+----------------------------------------------+---------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM240T100C5 for design "i2s_ns0921"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EPM240T100I5 is compatible
Info (176445): Device EPM240T100A5 is compatible
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Critical Warning (332012): Synopsys Design Constraints File file not found: 'i2s_ns0921.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info (332127): Assuming a default timing requirement
Info (332111): Found 4 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 1.000 bck_m
Info (332111): 1.000 I2C_to_GPIO:i2c|sclk
Info (332111): 1.000 I2C_to_GPIO:i2c|sda
Info (332111): 1.000 mclk_in
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186216): Automatically promoted some destinations of signal "mclk_in" to use Global clock in PIN 12 File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 4
Info (186217): Destination "mclk~0" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 5
Info (186216): Automatically promoted some destinations of signal "I2C_to_GPIO:i2c|sclk" to use Global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 38
Info (186217): Destination "I2C_to_GPIO:i2c|sclk" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 38
Info (186217): Destination "I2C_to_GPIO:i2c|start" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 20
Info (186217): Destination "I2C_to_GPIO:i2c|stop" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 20
Info (186216): Automatically promoted some destinations of signal "bck_m" to use Global clock File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 12
Info (186217): Destination "bck" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 6
Info (186217): Destination "bck_m" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 12
Info (186216): Automatically promoted some destinations of signal "I2C_to_GPIO:i2c|sda" to use Global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 38
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[7]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186217): Destination "I2C_to_GPIO:i2c|sda" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 38
Info (186217): Destination "I2C_to_GPIO:i2c|read_oper" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 31
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[1]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[0]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186217): Destination "I2C_to_GPIO:i2c|add_is_matching~2" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 31
Info (186217): Destination "I2C_to_GPIO:i2c|add_is_matching~3" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 31
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[2]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[3]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186217): Destination "I2C_to_GPIO:i2c|GPIO_output[4]" may be non-global or may not use global clock File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 132
Info (186218): Limited to 10 non-global destinations
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 4% of the available device resources
Info (170196): Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.21 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file /home/naoki/altera/i2s_ns0921/i2s_ns0921.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 1196 megabytes
Info: Processing ended: Fri Jul 16 09:27:43 2021
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /home/naoki/altera/i2s_ns0921/i2s_ns0921.fit.smsg.