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i2s_ns0921.map.rpt
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Analysis & Synthesis report for i2s_ns0921
Fri Jul 16 09:27:27 2021
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Multiplexer Restructuring Statistics (Restructuring Performed)
11. Parameter Settings for User Entity Instance: I2C_to_GPIO:i2c
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Jul 16 09:27:27 2021 ;
; Quartus Prime Version ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
; Revision Name ; i2s_ns0921 ;
; Top-level Entity Name ; i2s_ns0921 ;
; Family ; MAX II ;
; Total logic elements ; 98 ;
; Total pins ; 6 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM240T100C5 ; ;
; Top-level entity name ; i2s_ns0921 ; i2s_ns0921 ;
; Family name ; MAX II ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+---------+
; I2C_to_GPIO.v ; yes ; User Verilog HDL File ; /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v ; ;
; i2s_ns0921.v ; yes ; User Verilog HDL File ; /home/naoki/altera/i2s_ns0921/i2s_ns0921.v ; ;
+----------------------------------+-----------------+------------------------+---------------------------------------------+---------+
+--------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------------+
; Total logic elements ; 98 ;
; -- Combinational with no register ; 46 ;
; -- Register only ; 7 ;
; -- Combinational with a register ; 45 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 50 ;
; -- 3 input functions ; 20 ;
; -- 2 input functions ; 18 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 93 ;
; -- arithmetic mode ; 5 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 6 ;
; -- asynchronous clear/load mode ; 2 ;
; ; ;
; Total registers ; 52 ;
; Total logic cells in carry chains ; 6 ;
; I/O pins ; 6 ;
; Maximum fan-out node ; I2C_to_GPIO:i2c|sclk ;
; Maximum fan-out ; 33 ;
; Total fan-out ; 385 ;
; Average fan-out ; 3.70 ;
+---------------------------------------------+----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; |i2s_ns0921 ; 98 (29) ; 52 ; 0 ; 6 ; 0 ; 46 (17) ; 7 (1) ; 45 (11) ; 6 (6) ; 0 (0) ; |i2s_ns0921 ; work ;
; |I2C_to_GPIO:i2c| ; 69 (69) ; 40 ; 0 ; 0 ; 0 ; 29 (29) ; 6 (6) ; 34 (34) ; 0 (0) ; 0 (0) ; |i2s_ns0921|I2C_to_GPIO:i2c ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; I2C_to_GPIO:i2c|sda_out ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 52 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 2 ;
; Number of registers using Asynchronous Clear ; 2 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 14 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |i2s_ns0921|I2C_to_GPIO:i2c|GPIO_input_reg[2] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |i2s_ns0921|I2C_to_GPIO:i2c|count[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_to_GPIO:i2c ;
+----------------+---------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+---------+-----------------------------------+
; slave_address ; 1000001 ; Unsigned Binary ;
; n ; 8 ; Signed Integer ;
+----------------+---------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
Info: Processing started: Fri Jul 16 09:26:54 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2s_ns0921 -c i2s_ns0921
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file I2C_to_GPIO.v
Info (12023): Found entity 1: I2C_to_GPIO File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file i2s_ns0921.v
Info (12023): Found entity 1: i2s_ns0921 File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 1
Info (12127): Elaborating entity "i2s_ns0921" for the top level hierarchy
Info (12128): Elaborating entity "I2C_to_GPIO" for hierarchy "I2C_to_GPIO:i2c" File: /home/naoki/altera/i2s_ns0921/i2s_ns0921.v Line: 45
Warning (10036): Verilog HDL or VHDL warning at I2C_to_GPIO.v(31): object "sda_ack" assigned a value but never read File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 31
Warning (10036): Verilog HDL or VHDL warning at I2C_to_GPIO.v(33): object "start_reset" assigned a value but never read File: /home/naoki/altera/i2s_ns0921/I2C_to_GPIO.v Line: 33
Info (21057): Implemented 104 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 3 output pins
Info (21060): Implemented 1 bidirectional pins
Info (21061): Implemented 98 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 1145 megabytes
Info: Processing ended: Fri Jul 16 09:27:27 2021
Info: Elapsed time: 00:00:33
Info: Total CPU time (on all processors): 00:00:48