From f4ee3e0a468e3dc2cf8a3d5d135b09f9e7177a86 Mon Sep 17 00:00:00 2001 From: Malachy Lynch Date: Wed, 14 Feb 2024 12:38:23 +0000 Subject: [PATCH] Squashed 'mpfs_hal/' changes from 09dc9b6..c0a3883 c0a3883 feat(power saving): Self refresh 89de791 feat(power saving): Turn off unused hart's RAM 67fc10e feat(utility): Added L2 cache flush function caed9bf refactor(fpu enable): FPU is now enabled 2823bd6 feat(power saving): Turn off RAM 954cb08 add feature to initialize global constructor 618c8c1 turn on UART before its initialization 6c86dd9 compilation fix for CPP project: remove the extra volatile keyword 61b26de Added more detail in the Training Skip comment f240282 Added DDR Training skip in Renode git-subtree-dir: mpfs_hal git-subtree-split: c0a388341bf67f3315286f57b417cc6208241d5a --- common/mss_axiswitch.c | 2 +- common/mss_l2_cache.c | 95 ++++++- common/mss_l2_cache.h | 13 +- common/mss_mpu.h | 2 +- common/mss_peripherals.c | 13 + common/mss_peripherals.h | 37 ++- common/nwc/mss_ddr.c | 82 +++++- common/nwc/mss_ddr.h | 112 +++++--- common/nwc/mss_ddr_sgmii_phy_defs.h | 2 +- common/nwc/mss_ddr_sgmii_regs.h | 2 +- common/nwc/mss_ddr_test_pattern.c | 382 ++++++++++++++-------------- common/nwc/mss_io_config.h | 46 ++-- common/nwc/mss_scb_nwc_regs.h | 40 +-- mpfs_hal_version.h | 4 +- startup_gcc/mss_entry.S | 30 +-- startup_gcc/mss_utils.S | 87 ++++--- startup_gcc/newlib_stubs.c | 25 ++ startup_gcc/system_startup.c | 68 ++++- startup_gcc/system_startup.h | 12 +- 19 files changed, 703 insertions(+), 351 deletions(-) diff --git a/common/mss_axiswitch.c b/common/mss_axiswitch.c index f0abb90..7627f9f 100644 --- a/common/mss_axiswitch.c +++ b/common/mss_axiswitch.c @@ -168,7 +168,7 @@ int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num, if(burstiness_val == 0) { - return -1; + return -1; } else { diff --git a/common/mss_l2_cache.c b/common/mss_l2_cache.c index ed6d784..de82bbf 100644 --- a/common/mss_l2_cache.c +++ b/common/mss_l2_cache.c @@ -30,7 +30,7 @@ static const uint64_t g_init_marker = INIT_MARKER; static void check_config_l2_scratchpad(void); /***************************************************************************//** - * See hw_l2_scratch.h for details of how to use this function. + * See mss_l2_scratch.h for details of how to use this function. */ __attribute__((weak)) uint64_t end_l2_scratchpad_address(void) { @@ -39,7 +39,7 @@ __attribute__((weak)) uint64_t end_l2_scratchpad_address(void) } /***************************************************************************//** - * See hw_l2_scratch.h for details of how to use this function. + * See mss_l2_scratch.h for details of how to use this function. */ __attribute__((weak)) uint32_t num_cache_ways(void) { @@ -51,16 +51,36 @@ __attribute__((weak)) uint32_t num_cache_ways(void) } /***************************************************************************//** - * See hw_l2_scratch.h for details of how to use this function. + * See mss_l2_scratch.h for details of how to use this function. */ -__attribute__((weak)) uint32_t my_num_cache_ways(void) +__attribute__((weak)) uint32_t my_num_dcache_ways(uint32_t hartid) { uint32_t num_ways = 0U; uint32_t way_enable; uint32_t bit_index; - //todo: return for my hart, assuming e51 here - way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_E51_DCACHE; + for (uint32_t current_way = 0; current_way <= LIBERO_SETTING_WAY_ENABLE; current_way++) { + /* disable evictions from all but current_way */ + switch (hartid) + { + case 0: + way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_E51_DCACHE; + break; + case 1: + way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_1_DCACHE; + break; + case 2: + way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_2_DCACHE; + break; + case 3: + way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_3_DCACHE; + break; + case 4: + way_enable = (uint32_t)LIBERO_SETTING_WAY_MASK_U54_4_DCACHE; + break; + } + } + bit_index = 0U; while(bit_index < 16U) @@ -75,7 +95,7 @@ __attribute__((weak)) uint32_t my_num_cache_ways(void) } /***************************************************************************//** - * See mss_uart.h for details of how to use this function. + * See mss_l2_scratch.h for details of how to use this function. */ __attribute__((weak)) void config_l2_cache(void) { @@ -197,7 +217,6 @@ __attribute__((weak)) void config_l2_cache(void) mb(); } - /*============================================================================== * Configure the L2 scratchpad based on linker symbols: * __l2_scratchpad_vma_start @@ -233,3 +252,63 @@ static void check_config_l2_scratchpad(void) ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } + +/***************************************************************************//** + * See mss_l2_scratch.h for details of how to use this function. + */ +void flush_l2_cache(uint32_t hartid) +{ + /* + * flush L2 Cache, way-by-way + * see https://forums.sifive.com/t/flush-invalidate-l1-l2-on-the-u54-mc/4483/9 + * the thing to be wary of is the policy is random replacement by way, + * so there must be only 1 way enabled at a time... + * then, still need to go through ~2MiB (2MiB/16 per way) of reads to + * safely ensure the L2 is cleared... + */ + + for (uint32_t current_way = 0; current_way <= LIBERO_SETTING_WAY_ENABLE; current_way++) { + /* disable evictions from all but current_way */ + switch (hartid) + { + case 0: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_E51_DCACHE, current_way, __ATOMIC_RELAXED); + break; + case 1: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_1_DCACHE, current_way, __ATOMIC_RELAXED); + break; + case 2: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_2_DCACHE, current_way, __ATOMIC_RELAXED); + break; + case 3: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_3_DCACHE, current_way, __ATOMIC_RELAXED); + break; + case 4: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_4_DCACHE, current_way, __ATOMIC_RELAXED); + break; + } + + /* read 2MiB/16 from L2 zero device */ + for (uint64_t i = 0u; i < 131u*1024u; i+=8u) + { (void)*(volatile uint64_t *)(ZERO_DEVICE_BOTTOM + i); }; + } + /* restore WayMask values... */ + switch (hartid) + { + case 0: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_E51_DCACHE, LIBERO_SETTING_WAY_MASK_E51_DCACHE, __ATOMIC_RELAXED); + break; + case 1: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_1_DCACHE, LIBERO_SETTING_WAY_MASK_U54_1_DCACHE, __ATOMIC_RELAXED); + break; + case 2: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_2_DCACHE, LIBERO_SETTING_WAY_MASK_U54_2_DCACHE, __ATOMIC_RELAXED); + break; + case 3: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_3_DCACHE, LIBERO_SETTING_WAY_MASK_U54_3_DCACHE, __ATOMIC_RELAXED); + break; + case 4: + __atomic_store_8(&CACHE_CTRL->WAY_MASK_U54_4_DCACHE, LIBERO_SETTING_WAY_MASK_U54_4_DCACHE, __ATOMIC_RELAXED); + break; + } +} diff --git a/common/mss_l2_cache.h b/common/mss_l2_cache.h index 5c4583f..7b405bb 100644 --- a/common/mss_l2_cache.h +++ b/common/mss_l2_cache.h @@ -570,8 +570,19 @@ void config_l2_cache(void); */ uint8_t check_num_scratch_ways(uint64_t *start, uint64_t *end); +/***************************************************************************//** + Returns the number of cache ways + + */ uint32_t num_cache_ways(void); -uint32_t my_num_cache_ways(void); + +uint32_t my_num_dcache_ways(uint32_t hartid); + +/***************************************************************************//** + Flushes the L2 cache + + */ +void flush_l2_cache(uint32_t hartid); #ifdef __cplusplus } diff --git a/common/mss_mpu.h b/common/mss_mpu.h index 531b321..a69776d 100644 --- a/common/mss_mpu.h +++ b/common/mss_mpu.h @@ -103,7 +103,7 @@ typedef struct typedef struct { MPU_CFG PMPCFG[16U]; - __IO MPU_FailStatus_TypeDef STATUS; + MPU_FailStatus_TypeDef STATUS; } MPU_TypeDef; diff --git a/common/mss_peripherals.c b/common/mss_peripherals.c index 5b335fe..49d0dbd 100644 --- a/common/mss_peripherals.c +++ b/common/mss_peripherals.c @@ -183,3 +183,16 @@ __attribute__((weak)) uint32_t mss_get_apb_bus_cr(void) return (SYSREG->APBBUS_CR); } +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) void mss_turn_off_unused_ram_clks(void) +{ + CAN0_RAM_OFF_IF_NOT_CONFIGURED(); + CAN1_RAM_OFF_IF_NOT_CONFIGURED(); + USB_RAM_OFF_IF_NOT_CONFIGURED(); + MAC0_RAM_OFF_IF_NOT_CONFIGURED(); + MAC1_RAM_OFF_IF_NOT_CONFIGURED(); + MMC_RAM_OFF_IF_NOT_CONFIGURED(); + DDR_RAM_OFF_IF_NOT_CONFIGURED(); +} diff --git a/common/mss_peripherals.h b/common/mss_peripherals.h index 8dd1689..4311dda 100644 --- a/common/mss_peripherals.h +++ b/common/mss_peripherals.h @@ -82,9 +82,33 @@ typedef enum mss_peripherals_ { MSS_PERIPH_FIC0 = 32U, MSS_PERIPH_FIC1 = 33U, MSS_PERIPH_FIC2 = 34U, - MSS_PERIPH_FIC3 = 35U + MSS_PERIPH_FIC3 = 35U, + MSS_PERIPH_INVALID = 255U } mss_peripherals; +#ifndef LIBERO_SETTING_TURN_OFF_RAM_IF_NOT_USED +#define LIBERO_SETTING_TURN_OFF_RAM_IF_NOT_USED +#endif + +#ifndef LIBERO_SETTING_CONFIGURED_PERIPHERALS +#define LIBERO_SETTING_CONFIGURED_PERIPHERALS 0xFFFFFFFF +#endif + +#define CAN0_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (1U<<15U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<0U)) +#define CAN1_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (1U<<16U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<1U)) +#define USB_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (1U<<2U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U <<2U)) +#define MAC0_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (1U<<3U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<3U)) +#define MAC1_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (1U<<4U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<4U)) +#define MMC_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_CONFIGURED_PERIPHERALS\ + & (3U<<0U))==0U) (SYSREG->RAM_SHUTDOWN_CR |= (1U<<5U)) +#define DDR_RAM_OFF_IF_NOT_CONFIGURED() if((LIBERO_SETTING_DDRPHY_MODE &\ + DDRPHY_MODE_MASK) == DDR_OFF_MODE)\ + (SYSREG->RAM_SHUTDOWN_CR |= (1U<<7U)) /***************************************************************************//** This function is used to turn on or off a peripheral. If contexts have been @@ -162,6 +186,17 @@ void mss_set_apb_bus_cr(uint32_t reg_value); */ uint32_t mss_get_apb_bus_cr(void); +/***************************************************************************//** + This function is used to turn off RAM associated with peripherals that are + marked as unused in the MSS Configurator. + + Example: + @code + mss_turn_off_unused_ram_clks(); + @endcode + */ +void mss_turn_off_unused_ram_clks(void); + #ifdef __cplusplus } diff --git a/common/nwc/mss_ddr.c b/common/nwc/mss_ddr.c index 2899808..9bd729f 100644 --- a/common/nwc/mss_ddr.c +++ b/common/nwc/mss_ddr.c @@ -27,9 +27,11 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.4.023" +#define DDR_DRIVER_VERSION_STRING "0.4.024" const char DDR_DRIVER_VERSION[] = DDR_DRIVER_VERSION_STRING; /* Version | Comment */ +/* 0.4.024 | Self-refresh is disabled from UI, api functions added for */ +/* | turning self-refresh off and on. */ /* 0.4.023 | Changed default ADDCMD CLK push order for DDR4 to 0,45,90 */ /* 0.4.022 | Tidied comments and simulation reference- no code change */ /* 0.4.021 | Added options to increase post training tests during */ @@ -244,6 +246,57 @@ uint32_t noise_ena = 0x0; * Public Functions - API ******************************************************************************/ +void mpfs_hal_turn_ddr_selfrefresh_on(void) +{ + uint32_t chip_selects; + /* + * Turn on user setting for self refresh + * Self-refresh control. Causes the controller to put the selected SDRAM + * rank(chip select) into self-refresh mode at the next refresh event. Each + * bit in init self refresh corresponds to the selected rank; asserting init + * self refresh[0] puts the devices connected to cs n[0] into self refresh, + * init self refresh[1] for cs n[1] and so on. + */ + if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_RANK_MASK) == + DDRPHY_MODE_TWO_RANKS) + { + chip_selects = 3U; + } + else + { + chip_selects = 1U; + } + DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = chip_selects; +} + +void mpfs_hal_turn_ddr_selfrefresh_off(void) +{ + /* + * Turn on user setting for self refresh + */ + DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = 0U; +} + +uint32_t mpfs_hal_ddr_selfrefresh_status(void) +{ + uint32_t status = 1U; /* self refresh on */ + + if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_RANK_MASK) == DDRPHY_MODE_TWO_RANKS) + { + if( (DDRCFG->MC_BASE2.INIT_SELF_REFRESH_STATUS.INIT_SELF_REFRESH_STATUS & 3U) == 3U) + { + status = 0U; + } + } + else + { + if((DDRCFG->MC_BASE2.INIT_SELF_REFRESH_STATUS.INIT_SELF_REFRESH_STATUS & 1U) == 1U) + { + status = 0U; + } + } + return status; +} /***************************************************************************//** * ddr_state_machine(DDR_SS_COMMAND) @@ -325,6 +378,26 @@ static uint32_t ddr_setup(void) ddr_type = LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_MASK; +/* + * Usually in Renode we want to skip DDR training, as it is slow and does not + * do anything useful. If the user wants to explicitly simulate the training, + * then RENODE_SIM_DDR_TRAINING should be defined. + * The Training skip is achieved by reading from a register that should always + * return 0's in Hardware. In this case, the MPFS_DDRMock module will return + * a known pattern that will let us know we are in a simulation, and will skip + * the training. + * The RPC_RESET_MAIN_PLL register can usually only return 0x00 or 0x01, as + * the other bits are set to Rreturns0. This signature string "REND" will only + * ever be read when connected to the Renode MPFS_DDRMock module. + */ +#ifndef RENODE_SIM_DDR_TRAINING + if (0x52454E44 == CFG_DDR_SGMII_PHY->RPC_RESET_MAIN_PLL.RPC_RESET_MAIN_PLL) + { + ret_status |= DDR_SETUP_DONE; + ddr_training_state = DDR_TRAINING_FINISHED; + } +#endif + switch (ddr_training_state) { case DDR_TRAINING_INIT: @@ -545,7 +618,7 @@ static uint32_t ddr_setup(void) if (ddr_type == LPDDR4) { - /* vrgen, modify during write leveling, turns off ODT */ + /* vrgen, modify during write leveling, turns off ODT */ CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS =\ (dpc_bits & ~DDR_DPC_VRGEN_H_MASK)| (DPC_VRGEN_H_LPDDR4_WR_LVL_VAL << DDR_DPC_VRGEN_H_SHIFT); CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = 0x0; @@ -4056,8 +4129,7 @@ static void init_ddrc(void) LIBERO_SETTING_CFG_CAL_READ_PERIOD; DDRCFG->MC_BASE2.CFG_NUM_CAL_READS.CFG_NUM_CAL_READS =\ LIBERO_SETTING_CFG_NUM_CAL_READS; - DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH =\ - LIBERO_SETTING_INIT_SELF_REFRESH; + DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH = 0U; DDRCFG->MC_BASE2.INIT_POWER_DOWN.INIT_POWER_DOWN =\ LIBERO_SETTING_INIT_POWER_DOWN; DDRCFG->MC_BASE2.INIT_FORCE_WRITE.INIT_FORCE_WRITE =\ @@ -4692,6 +4764,7 @@ MSS_DDR_user_commands #endif #ifdef DEBUG_DDR_INIT +#ifdef DEBUG_DDR_DDRCFG void debug_read_ddrcfg(void) { (void)print_reg_array(g_debug_uart , @@ -4742,6 +4815,7 @@ void debug_read_ddrcfg(void) return; } #endif +#endif const uint8_t REFCLK_OFFSETS[][5U] = { diff --git a/common/nwc/mss_ddr.h b/common/nwc/mss_ddr.h index 36ea7b0..2a2351e 100644 --- a/common/nwc/mss_ddr.h +++ b/common/nwc/mss_ddr.h @@ -1249,20 +1249,12 @@ typedef struct sweep_index_{ /***************************************************************************//** */ -uint8_t -MSS_DDR_init_simulation -( - void -); +uint8_t MSS_DDR_init_simulation(void); /***************************************************************************//** */ -uint8_t -MSS_DDR_training -( - uint8_t ddr_type -); +uint8_t MSS_DDR_training(uint8_t ddr_type); /***************************************************************************//** @@ -1290,34 +1282,26 @@ MSS_DDR_training @endcode */ -uint32_t -ddr_state_machine -( - DDR_SS_COMMAND command -); +uint32_t ddr_state_machine(DDR_SS_COMMAND command); /***************************************************************************//** - The debug_read_ddrcfg() prints out the ddrcfg register values + The setup_ddr_segments() sets up seg regs @return - This function returns status, see DDR_SS_STATUS enum + none Example: @code - debug_read_ddrcfg(); + setup_ddr_segments(DEFAULT_SEG_SETUP); @endcode */ -void -debug_read_ddrcfg -( - void -); +void setup_ddr_segments(SEG_SETUP option); /***************************************************************************//** - The setup_ddr_segments() sets up seg regs + The clear_bootup_cache_ways() sets up seg regs @return none @@ -1325,19 +1309,85 @@ debug_read_ddrcfg Example: @code - setup_ddr_segments(DEFAULT_SEG_SETUP); + clear_bootup_cache_ways(DEFAULT_SEG_SETUP); @endcode */ -void -setup_ddr_segments -( - SEG_SETUP option -); +void clear_bootup_cache_ways(void); + +/***************************************************************************//** + The fill_cache_new_seg_address() + + @return + none + + Example: + @code + + fill_cache_new_seg_address(DEFAULT_SEG_SETUP); + @endcode + + */ char * fill_cache_new_seg_address(void *dest, void *dest_end); -void clear_bootup_cache_ways(void); + +/***************************************************************************//** + The mpfs_hal_turn_ddr_selfrefresh_on(void) flushes cache and turns on self + refresh. When DDR is in self refresh mode, less power is consumed by the + memory. Data is retained. You can not write or read from the DDR when + self-refresh is on. + + + @return + none + + Example: + @code + + mpfs_hal_turn_ddr_selfrefresh_on(DEFAULT_SEG_SETUP); + + @endcode + + */ +void mpfs_hal_turn_ddr_selfrefresh_on(void); + +/***************************************************************************//** + The mpfs_hal_turn_ddr_selfrefresh_off() + + @return + none + + Example: + @code + + mpfs_hal_turn_ddr_selfrefresh_off(); + + @endcode + + */ +void mpfs_hal_turn_ddr_selfrefresh_off(void); + +/***************************************************************************//** + The mpfs_hal_ddr_selfrefresh_status() + + @return + none + + Example: + @code + + status = mpfs_hal_ddr_selfrefresh_status(); + + if(status != 0U) + { + printf("self refresh is on\n"); + } + + @endcode + + */ +uint32_t mpfs_hal_ddr_selfrefresh_status(void); #ifdef __cplusplus diff --git a/common/nwc/mss_ddr_sgmii_phy_defs.h b/common/nwc/mss_ddr_sgmii_phy_defs.h index efc7bc9..cc8f7f3 100644 --- a/common/nwc/mss_ddr_sgmii_phy_defs.h +++ b/common/nwc/mss_ddr_sgmii_phy_defs.h @@ -432,7 +432,7 @@ typedef union{ /*!< PLL_ } CFG_DDR_SGMII_PHY_PLL_PHADJ_MAIN_TypeDef; typedef union{ /*!< SSCG_REG_0_MAIN register definition*/ - __IO uint32_t SSCG_REG_0_MAIN; /* todo: verify should be r/w, it is not in source file from Duolog */ + __IO uint32_t SSCG_REG_0_MAIN; struct { __I uint32_t DIVVAL :6; diff --git a/common/nwc/mss_ddr_sgmii_regs.h b/common/nwc/mss_ddr_sgmii_regs.h index a5ec656..042fcc8 100644 --- a/common/nwc/mss_ddr_sgmii_regs.h +++ b/common/nwc/mss_ddr_sgmii_regs.h @@ -4327,7 +4327,7 @@ typedef struct typedef struct { __IO DDR_CSR_APB_PHY_RESET_CONTROL_TypeDef PHY_RESET_CONTROL; /*!< Offset: 0x0 */ - __IO DDR_CSR_APB_PHY_PC_RANK_TypeDef PHY_PC_RANK; /*!< Offset: 0x4 */ + __IO DDR_CSR_APB_PHY_PC_RANK_TypeDef PHY_PC_RANK; /*!< Offset: 0x4 */ __IO DDR_CSR_APB_PHY_RANKS_TO_TRAIN_TypeDef PHY_RANKS_TO_TRAIN; /*!< Offset: 0x8 */ __IO DDR_CSR_APB_PHY_WRITE_REQUEST_TypeDef PHY_WRITE_REQUEST; /*!< Offset: 0xc */ __I DDR_CSR_APB_PHY_WRITE_REQUEST_DONE_TypeDef PHY_WRITE_REQUEST_DONE; /*!< Offset: 0x10 */ diff --git a/common/nwc/mss_ddr_test_pattern.c b/common/nwc/mss_ddr_test_pattern.c index 7d460fd..682d1da 100644 --- a/common/nwc/mss_ddr_test_pattern.c +++ b/common/nwc/mss_ddr_test_pattern.c @@ -14,197 +14,197 @@ const uint32_t ddr_test_pattern[768] = { 0x48b301bc, 0x79330115, 0xf5330139, 0x693301bc, - 0x893b00a9, 0x093b0128, 0x0d3b00c9, 0x551b00cd, - 0x161b0077, 0x8d510197, 0x0127581b, 0x00e7161b, - 0x01066633, 0x561b8d31, 0x8d310037, 0x8f3b9da9, - 0xd61b01e5, 0x959b0112, 0xd51b00f2, 0x8e4d0132, - 0x00d2959b, 0x8e2d8dc9, 0x00a2d29b, 0x005642b3, - 0xa4507637, 0x005f0f3b, 0x00dac5b3, 0xceb6061b, - 0x00cf063b, 0x01a5f5b3, 0x0155c5b3, 0x01460a3b, - 0x00ba0a3b, 0x01ad161b, 0x006d559b, 0x015d151b, - 0x561b8dd1, 0x8e4900bd, 0x551b8db1, 0x161b019d, - 0x8e49007d, 0x05bb8db1, 0x161b00ba, 0x5a1b01e9, - 0x151b0029, 0x6a330139, 0x561b00ca, 0x8e4900d9, - 0x00ca4a33, 0x0169551b, 0x00a9161b, 0x4a338e49, - 0xe63300ca, 0xf533012d, 0x7633012d, 0x8e490196, - 0x00ca0a3b, 0x0077d51b, 0x0197961b, 0x00ba0a3b, - 0x00b989bb, 0x959b8d51, 0xd61b00e7, 0x8e4d0127, - 0xd59b8e29, 0x8e2d0037, 0xbef9a5b7, 0x3f75859b, - 0x9f319f2d, 0x01770bbb, 0x011fd61b, 0x00ff971b, - 0x013fd59b, 0x961b8f51, 0x8e4d00df, 0xdf9b8f31, - 0x4fb300af, 0xc73301f7, 0x8fbb01a6, 0x773301fb, - 0x8f350137, 0x015f8abb, 0x00ea8abb, 0x01a9961b, - 0x0069d71b, 0x0159959b, 0xd61b8f51, 0x8e4d00b9, - 0xd59b8f31, 0x961b0199, 0x8e4d0079, 0x873b8f31, - 0x161b00ea, 0x5a9b01ea, 0x159b002a, 0xeab3013a, - 0x561b00ca, 0x8e4d00da, 0x00cacab3, 0x016a559b, - 0x00aa161b, 0xcab38e4d, 0x663300ca, 0x75b30149, - 0x76330149, 0x8e4d01b6, 0x00ca8abb, 0x00ea8abb, - 0x00ec8cbb, 0x019b161b, 0x007b571b, 0x559b8f51, - 0x161b012b, 0x8e4d00eb, 0x5b1b8f31, 0x4b33003b, - 0x87370167, 0x071bc671, 0x9fb98f27, 0x016787bb, - 0x171b9cbd, 0x579b00ff, 0x561b011f, 0x8f5d013f, - 0x00df179b, 0x8f3d8fd1, 0x00af5f1b, 0x01e74f33, - 0x013d4733, 0x01e48f3b, 0x01977733, 0x01a74733, - 0x00df06bb, 0xd79b9eb9, 0x971b006c, 0x961b01ac, - 0x8fd9015c, 0x00bcd71b, 0x8fb98f51, 0x019cd61b, - 0x007c971b, 0x8fb98f51, 0x971b9ebd, 0xd79b01ea, - 0x961b002a, 0x8fd9013a, 0x00dad71b, 0x8fb98f51, - 0x016ad61b, 0x00aa971b, 0x8fb98f51, 0x015a6733, - 0x015a7633, 0x01277733, 0x9fb98f51, 0x9fb96722, - 0x9fb56702, 0x67e2c71c, 0x01578abb, 0x262377c2, - 0x8a3b0157, 0x77e20147, 0x01472823, 0x0127893b, - 0x2a2367c2, 0x8dbb0127, 0x778201b7, 0x00dd86bb, - 0x8cbbcf14, 0x77a20197, 0x01972e23, 0x013789bb, - 0x20236786, 0x8d3b0337, 0x222301a7, 0x742a03a7, - 0x696a748a, 0x6a2a69ca, 0x7b666a8a, 0x7c267bc6, - 0x6d667c86, 0x614d6dc6, 0xe7b78082, 0x87936a09, - 0xc51c6677, 0xbb67b7b7, 0xe8578793, 0xf7b7c55c, - 0x87933c6e, 0xc91c3727, 0xa54ff7b7, 0x53a78793, - 0x57b7c95c, 0x8793510e, 0xcd1c27f7, 0x9b0577b7, - 0x88c78793, 0xe7b7cd5c, 0x87931f83, 0xd11c9ab7, - 0x5be0d7b7, 0xd1978793, 0x00052023, 0x00052223, - 0x8082d15c, 0x7139ce79, 0xf426f822, 0xe852f04a, - 0xec4efc06, 0xe05ae456, 0x84aa411c, 0x073b892e, - 0xc11800f6, 0xfa138432, 0x756303f7, 0x415c00c7, - 0xc15c2785, 0x020a0f63, 0x04000993, 0x414989bb, - 0x0009879b, 0x02f46763, 0x8a931982, 0xd9930284, - 0x85ca0209, 0x8533864e, 0x50ef014a, 0x043b4b00, - 0x85d60144, 0xc0ef8526, 0x041bf7cf, 0x994efc04, - 0x89ca4a01, 0x00890b3b, 0x03f00a93, 0x85cea039, - 0xc0ef8526, 0x8993f60f, 0x07bb0409, 0xe8e3413b, - 0x579bfefa, 0x06130064, 0x063bfc00, 0x559b02f6, - 0x059a0064, 0x9e2195ca, 0x0006079b, 0x7442c38d, - 0x02848513, 0x74a270e2, 0x69e27902, 0x6b026aa2, - 0x6a429552, 0x92011602, 0x506f6121, 0x70e24400, - 0x74a27442, 0x69e27902, 0x6aa26a42, 0x61216b02, - 0x80828082, 0xf0227179, 0xf406ec26, 0x41544110, - 0x579b84ae, 0x969b01d6, 0x8fd50036, 0x0186d59b, - 0x0106d69b, 0x00d104a3, 0x0087d693, 0x0ff6f693, - 0x171b07a2, 0x8fd50036, 0x00f11523, 0x0187579b, - 0x00f10623, 0x0107579b, 0x06a38321, 0x771300f1, - 0x17930ff7, 0x8f5d00b6, 0x00b10423, 0x00e11723, - 0x03f67613, 0x03700793, 0xe763842a, 0x079312c7, - 0x863b0380, 0x852240c7, 0x00025597, 0x19858593, - 0xea5ff0ef, 0x8522002c, 0xf0ef4621, 0x4783e9bf, - 0x802300b4, 0x578300f4, 0x80a300a4, 0x441c00f4, - 0x0087d79b, 0x00f48123, 0x81a3441c, 0x478300f4, - 0x822300f4, 0x578300f4, 0x82a300e4, 0x445c00f4, - 0x0087d79b, 0x00f48323, 0x83a3445c, 0x478300f4, - 0x84230134, 0x578300f4, 0x84a30124, 0x481c00f4, - 0x0087d79b, 0x00f48523, 0x85a3481c, 0x478300f4, - 0xb303679c, 0x04e30407, 0x8522fe03, 0x60a26402, - 0x83020141, 0xe0221141, 0x7d1ce406, 0xef89842a, - 0x4501643c, 0xb303679c, 0x0d630287, 0x85220003, - 0x60a26402, 0x83020141, 0x679c67bc, 0xd3ed67bc, - 0xdd799782, 0x640260a2, 0x80820141, 0x679c653c, - 0x0307b303, 0x00030363, 0x45018302, 0x711d8082, - 0x102cf42e, 0xf832ec06, 0xe0bafc36, 0xe8c2e4be, - 0xe42eecc6, 0x261240ef, 0x612560e2, 0x11418082, - 0xe406e022, 0x842a611c, 0xc7914fbc, 0x70ef6128, - 0x30239d6f, 0x643c0404, 0x53fc679c, 0x6828c791, - 0x9c4f70ef, 0x04043823, 0xcf897c1c, 0x53386398, - 0x67bce709, 0x57fc679c, 0x6c28c791, 0x9a8f70ef, - 0x04043c23, 0x09042783, 0x177d777d, 0x60a28ff9, - 0x08f42823, 0x01416402, 0x71798082, 0xf406f022, - 0xe84aec26, 0xe052e44e, 0xc9795429, 0x09052783, - 0x440184aa, 0xc7e98b85, 0x00053983, 0xf0ef892e, - 0x842af4ff, 0x864aed55, 0x85264581, 0x0c6000ef, - 0xed0d842a, 0x0289b703, 0x00197a13, 0xa783cb29, - 0x77b30709, 0xf79300f9, 0xe7b36007, 0xc3a10147, - 0x97028526, 0x6490cd0d, 0x00029597, 0x43058593, - 0x0002c517, 0xb7850513, 0xf17ff0ef, 0xf0ef8526, - 0x842aec7f, 0x6490c535, 0x00029597, 0x41058593, - 0x0002c517, 0xbc850513, 0xef7ff0ef, 0x7c9ca891, - 0x639cc39d, 0xc3856bbc, 0x97828526, 0xcd01842a, - 0x95976490, 0x85930002, 0xc5173e65, 0x05130002, - 0xf0efb6e5, 0xa583ecdf, 0x79330709, 0x791300b9, - 0x69336009, 0x0d630149, 0x85260009, 0xed3ff0ef, - 0xac2357fd, 0xa78308f4, 0x9bf90904, 0x08f4a823, - 0x852270a2, 0x64e27402, 0x69a26942, 0x61456a02, - 0x71798082, 0xe84af022, 0xf406e44e, 0x7938ec26, - 0x892e87aa, 0x89b26304, 0xf8070513, 0xf8048493, - 0x07078413, 0x08050793, 0x00879463, 0xa8394501, - 0x00090a63, 0x8763611c, 0x60dc0127, 0x84938526, - 0xb7cdf807, 0xf0ef85ce, 0xd965ec5f, 0x740270a2, - 0x694264e2, 0x614569a2, 0x11018082, 0xec06e822, - 0x7508842a, 0x860a468d, 0x0002f597, 0x73858593, - 0x488000ef, 0x8522e911, 0x800ff0ef, 0xc11c4782, - 0xc51c4792, 0xc15c47a2, 0xf0ef8522, 0x60e2eb2f, - 0x61056442, 0x715d8082, 0xf84ae0a2, 0xe486f44e, - 0xf052fc26, 0xe85aec56, 0x653ce45e, 0x458189ae, - 0x842a679c, 0x63848932, 0x867ff0ef, 0x09042783, - 0x0693862a, 0x8b850200, 0x0693c399, 0x601c02b0, - 0x451785a6, 0x05130003, 0x63980265, 0x4a1784ce, - 0x0a130003, 0x40ef05aa, 0x4a977e02, 0x8a930003, - 0x4b17046a, 0x0b130003, 0x4b97036b, 0x8b930003, - 0xd063026b, 0x640c0404, 0x0002d517, 0xe6850513, - 0x0019191b, 0x7b2240ef, 0x29857824, 0x07040413, - 0xf8048493, 0x08048793, 0x02f41c63, 0x640660a6, - 0x85a64601, 0xb0ef8522, 0x86aa54f1, 0x85d2864e, - 0xa0ef855a, 0x8b9b4852, 0x86520019, 0x852285a6, - 0xa95ff0ef, 0x85a689de, 0x8522864a, 0x7601b0ef, - 0xbb7d84aa, 0x854e75a2, 0x45f2a0ef, 0x85d2bd69, - 0xa0ef854e, 0xb5e14552, 0x651785ee, 0x05130003, - 0x83635765, 0x855a000a, 0x43f2a0ef, 0x854e85d2, - 0x4372a0ef, 0xb7192a85, 0x856685ee, 0x000a8363, - 0xa0ef855a, 0x85d24252, 0xa0ef854e, 0x2a8541d2, - 0x9863bf25, 0x86560147, 0xe42e8522, 0x99fff0ef, - 0x865e65a2, 0xb0ef8522, 0x85aa6f61, 0x4158b799, - 0x00ff0637, 0x0187569b, 0x0187179b, 0x169b8fd5, - 0x8ef10087, 0x66c18fd5, 0xf0068693, 0x0087571b, - 0x8fd98f75, 0x93811782, 0x8082953e, 0xec4e7139, - 0x89aae852, 0x85328a2e, 0x00034597, 0xac058593, - 0xf04af426, 0xfc06e456, 0x8ab2f822, 0x84ba8936, - 0x00f290ef, 0x66c1e539, 0x85ce8652, 0x80ef842a, - 0x571b0132, 0x179b0185, 0x8fd90185, 0x00ff06b7, - 0x0085171b, 0x8fd98f75, 0x551b6741, 0x07130085, - 0x8d79f007, 0x20238d5d, 0x479100a9, 0x70e2c09c, - 0x74428522, 0x790274a2, 0x6a4269e2, 0x61216aa2, - 0xe5978082, 0x85930003, 0x855657e5, 0x7b2290ef, - 0xe909842a, 0x864a66c1, 0x854e85d2, 0x37d200ef, - 0xb7e947d1, 0x0003e597, 0x56458593, 0x90ef8556, - 0x842a7902, 0x66c1e911, 0x85d2864a, 0x40ef854e, - 0x07936302, 0xb75d0200, 0x00030597, 0x5b058593, - 0x90ef8556, 0x842a76c2, 0x66c1e909, 0x85d2864a, - 0xf0ef854e, 0x47c112c1, 0x547db751, 0x7131b749, - 0xf526f922, 0xed4ef14a, 0xe556e952, 0xfcdee15a, - 0xf4e6f8e2, 0xeceef0ea, 0xfd068936, 0x89ae84aa, - 0xb0ef8a32, 0x842a64e1, 0x00036b17, 0x168b0b13, - 0x02010b93, 0x00033c17, 0xb64c0c13, 0x03010a93, - 0x01c10c93, 0x02810d13, 0x01810d93, 0x5e632901, - 0x57e10004, 0x00f40663, 0x450557d5, 0x0ef41563, - 0x00036917, 0x1b090913, 0x4601a855, 0x852685a2, - 0x3351b0ef, 0x855ae42a, 0x740290ef, 0x862a67a2, - 0x853e85da, 0x6ea290ef, 0x865ee921, 0x852685a2, - 0xe5aff0ef, 0x0e051763, 0x85627582, 0x24b2a0ef, - 0x661786d6, 0x06130003, 0x85a22166, 0xb0ef8526, - 0xc90d75b1, 0x47915742, 0x02f71663, 0xc39d411c, - 0x00036517, 0x20850513, 0x21f2a0ef, 0x00036517, - 0x20c50513, 0xdf3fc0ef, 0x852685a2, 0x5b41b0ef, - 0xb7b5842a, 0x866a86e6, 0x852685a2, 0xe26ff0ef, - 0x7602e541, 0x86d6876e, 0x855285ca, 0xe21ff0ef, - 0x47e2e53d, 0x1f634672, 0x75a204f6, 0x90ef8556, - 0xdd4d0172, 0x00036917, 0x15c90913, 0x460185a2, - 0xb0ef8526, 0x842a2831, 0x85ce4601, 0xb0ef8526, - 0x86aa2771, 0x85ca8622, 0x00036517, 0x1a850513, - 0x1a72a0ef, 0x70ea4501, 0x74aa744a, 0x69ea790a, - 0x6aaa6a4a, 0x7be66b0a, 0x7ca67c46, 0x6de67d06, - 0x80826129, 0x00036917, 0x11c90913, 0x6917bf45, - 0x09130003, 0xb75d12a9, 0x00036917, 0x0d890913, - 0x6917bf71, 0x09130003, 0xbf490ae9, 0x00347179, - 0xf022860a, 0xf406ec26, 0x842ae84a, 0xf0ef84ae, - 0xcd1dcbef, 0x45814601, 0xb0ef8522, 0x892a1fb1, - 0x85a64601, 0xb0ef8522, 0x86aa1ef1, 0x6597864a, - 0x85930003, 0x6517ffa5, 0x05130003, 0xa0ef0125, - 0x45011192, 0x740270a2, 0x694264e2, 0x80826145, - 0x660266a2, 0x852285a6, 0xe17ff0ef, 0x715db7e5, - 0x00037597, 0xe5858593, 0xe486fc26, 0xf84ae0a2, - 0xf052f44e, 0xe85aec56, 0xc0ef84aa, 0x5a6301c1, - 0xc0ef0205, 0x862a3421, 0x00037597, 0xe3058593, - 0x00036517, 0x11050513, 0x0bf2a0ef, 0x60a64501, - 0x74e26406, 0x79a27942, 0x6ae27a02, 0x61616b42, - 0x842a8082, 0x651785a6, 0x05130003, 0xa0efa325 + 0x893b00a9, 0x093b0128, 0x0d3b00c9, 0x551b00cd, + 0x161b0077, 0x8d510197, 0x0127581b, 0x00e7161b, + 0x01066633, 0x561b8d31, 0x8d310037, 0x8f3b9da9, + 0xd61b01e5, 0x959b0112, 0xd51b00f2, 0x8e4d0132, + 0x00d2959b, 0x8e2d8dc9, 0x00a2d29b, 0x005642b3, + 0xa4507637, 0x005f0f3b, 0x00dac5b3, 0xceb6061b, + 0x00cf063b, 0x01a5f5b3, 0x0155c5b3, 0x01460a3b, + 0x00ba0a3b, 0x01ad161b, 0x006d559b, 0x015d151b, + 0x561b8dd1, 0x8e4900bd, 0x551b8db1, 0x161b019d, + 0x8e49007d, 0x05bb8db1, 0x161b00ba, 0x5a1b01e9, + 0x151b0029, 0x6a330139, 0x561b00ca, 0x8e4900d9, + 0x00ca4a33, 0x0169551b, 0x00a9161b, 0x4a338e49, + 0xe63300ca, 0xf533012d, 0x7633012d, 0x8e490196, + 0x00ca0a3b, 0x0077d51b, 0x0197961b, 0x00ba0a3b, + 0x00b989bb, 0x959b8d51, 0xd61b00e7, 0x8e4d0127, + 0xd59b8e29, 0x8e2d0037, 0xbef9a5b7, 0x3f75859b, + 0x9f319f2d, 0x01770bbb, 0x011fd61b, 0x00ff971b, + 0x013fd59b, 0x961b8f51, 0x8e4d00df, 0xdf9b8f31, + 0x4fb300af, 0xc73301f7, 0x8fbb01a6, 0x773301fb, + 0x8f350137, 0x015f8abb, 0x00ea8abb, 0x01a9961b, + 0x0069d71b, 0x0159959b, 0xd61b8f51, 0x8e4d00b9, + 0xd59b8f31, 0x961b0199, 0x8e4d0079, 0x873b8f31, + 0x161b00ea, 0x5a9b01ea, 0x159b002a, 0xeab3013a, + 0x561b00ca, 0x8e4d00da, 0x00cacab3, 0x016a559b, + 0x00aa161b, 0xcab38e4d, 0x663300ca, 0x75b30149, + 0x76330149, 0x8e4d01b6, 0x00ca8abb, 0x00ea8abb, + 0x00ec8cbb, 0x019b161b, 0x007b571b, 0x559b8f51, + 0x161b012b, 0x8e4d00eb, 0x5b1b8f31, 0x4b33003b, + 0x87370167, 0x071bc671, 0x9fb98f27, 0x016787bb, + 0x171b9cbd, 0x579b00ff, 0x561b011f, 0x8f5d013f, + 0x00df179b, 0x8f3d8fd1, 0x00af5f1b, 0x01e74f33, + 0x013d4733, 0x01e48f3b, 0x01977733, 0x01a74733, + 0x00df06bb, 0xd79b9eb9, 0x971b006c, 0x961b01ac, + 0x8fd9015c, 0x00bcd71b, 0x8fb98f51, 0x019cd61b, + 0x007c971b, 0x8fb98f51, 0x971b9ebd, 0xd79b01ea, + 0x961b002a, 0x8fd9013a, 0x00dad71b, 0x8fb98f51, + 0x016ad61b, 0x00aa971b, 0x8fb98f51, 0x015a6733, + 0x015a7633, 0x01277733, 0x9fb98f51, 0x9fb96722, + 0x9fb56702, 0x67e2c71c, 0x01578abb, 0x262377c2, + 0x8a3b0157, 0x77e20147, 0x01472823, 0x0127893b, + 0x2a2367c2, 0x8dbb0127, 0x778201b7, 0x00dd86bb, + 0x8cbbcf14, 0x77a20197, 0x01972e23, 0x013789bb, + 0x20236786, 0x8d3b0337, 0x222301a7, 0x742a03a7, + 0x696a748a, 0x6a2a69ca, 0x7b666a8a, 0x7c267bc6, + 0x6d667c86, 0x614d6dc6, 0xe7b78082, 0x87936a09, + 0xc51c6677, 0xbb67b7b7, 0xe8578793, 0xf7b7c55c, + 0x87933c6e, 0xc91c3727, 0xa54ff7b7, 0x53a78793, + 0x57b7c95c, 0x8793510e, 0xcd1c27f7, 0x9b0577b7, + 0x88c78793, 0xe7b7cd5c, 0x87931f83, 0xd11c9ab7, + 0x5be0d7b7, 0xd1978793, 0x00052023, 0x00052223, + 0x8082d15c, 0x7139ce79, 0xf426f822, 0xe852f04a, + 0xec4efc06, 0xe05ae456, 0x84aa411c, 0x073b892e, + 0xc11800f6, 0xfa138432, 0x756303f7, 0x415c00c7, + 0xc15c2785, 0x020a0f63, 0x04000993, 0x414989bb, + 0x0009879b, 0x02f46763, 0x8a931982, 0xd9930284, + 0x85ca0209, 0x8533864e, 0x50ef014a, 0x043b4b00, + 0x85d60144, 0xc0ef8526, 0x041bf7cf, 0x994efc04, + 0x89ca4a01, 0x00890b3b, 0x03f00a93, 0x85cea039, + 0xc0ef8526, 0x8993f60f, 0x07bb0409, 0xe8e3413b, + 0x579bfefa, 0x06130064, 0x063bfc00, 0x559b02f6, + 0x059a0064, 0x9e2195ca, 0x0006079b, 0x7442c38d, + 0x02848513, 0x74a270e2, 0x69e27902, 0x6b026aa2, + 0x6a429552, 0x92011602, 0x506f6121, 0x70e24400, + 0x74a27442, 0x69e27902, 0x6aa26a42, 0x61216b02, + 0x80828082, 0xf0227179, 0xf406ec26, 0x41544110, + 0x579b84ae, 0x969b01d6, 0x8fd50036, 0x0186d59b, + 0x0106d69b, 0x00d104a3, 0x0087d693, 0x0ff6f693, + 0x171b07a2, 0x8fd50036, 0x00f11523, 0x0187579b, + 0x00f10623, 0x0107579b, 0x06a38321, 0x771300f1, + 0x17930ff7, 0x8f5d00b6, 0x00b10423, 0x00e11723, + 0x03f67613, 0x03700793, 0xe763842a, 0x079312c7, + 0x863b0380, 0x852240c7, 0x00025597, 0x19858593, + 0xea5ff0ef, 0x8522002c, 0xf0ef4621, 0x4783e9bf, + 0x802300b4, 0x578300f4, 0x80a300a4, 0x441c00f4, + 0x0087d79b, 0x00f48123, 0x81a3441c, 0x478300f4, + 0x822300f4, 0x578300f4, 0x82a300e4, 0x445c00f4, + 0x0087d79b, 0x00f48323, 0x83a3445c, 0x478300f4, + 0x84230134, 0x578300f4, 0x84a30124, 0x481c00f4, + 0x0087d79b, 0x00f48523, 0x85a3481c, 0x478300f4, + 0xb303679c, 0x04e30407, 0x8522fe03, 0x60a26402, + 0x83020141, 0xe0221141, 0x7d1ce406, 0xef89842a, + 0x4501643c, 0xb303679c, 0x0d630287, 0x85220003, + 0x60a26402, 0x83020141, 0x679c67bc, 0xd3ed67bc, + 0xdd799782, 0x640260a2, 0x80820141, 0x679c653c, + 0x0307b303, 0x00030363, 0x45018302, 0x711d8082, + 0x102cf42e, 0xf832ec06, 0xe0bafc36, 0xe8c2e4be, + 0xe42eecc6, 0x261240ef, 0x612560e2, 0x11418082, + 0xe406e022, 0x842a611c, 0xc7914fbc, 0x70ef6128, + 0x30239d6f, 0x643c0404, 0x53fc679c, 0x6828c791, + 0x9c4f70ef, 0x04043823, 0xcf897c1c, 0x53386398, + 0x67bce709, 0x57fc679c, 0x6c28c791, 0x9a8f70ef, + 0x04043c23, 0x09042783, 0x177d777d, 0x60a28ff9, + 0x08f42823, 0x01416402, 0x71798082, 0xf406f022, + 0xe84aec26, 0xe052e44e, 0xc9795429, 0x09052783, + 0x440184aa, 0xc7e98b85, 0x00053983, 0xf0ef892e, + 0x842af4ff, 0x864aed55, 0x85264581, 0x0c6000ef, + 0xed0d842a, 0x0289b703, 0x00197a13, 0xa783cb29, + 0x77b30709, 0xf79300f9, 0xe7b36007, 0xc3a10147, + 0x97028526, 0x6490cd0d, 0x00029597, 0x43058593, + 0x0002c517, 0xb7850513, 0xf17ff0ef, 0xf0ef8526, + 0x842aec7f, 0x6490c535, 0x00029597, 0x41058593, + 0x0002c517, 0xbc850513, 0xef7ff0ef, 0x7c9ca891, + 0x639cc39d, 0xc3856bbc, 0x97828526, 0xcd01842a, + 0x95976490, 0x85930002, 0xc5173e65, 0x05130002, + 0xf0efb6e5, 0xa583ecdf, 0x79330709, 0x791300b9, + 0x69336009, 0x0d630149, 0x85260009, 0xed3ff0ef, + 0xac2357fd, 0xa78308f4, 0x9bf90904, 0x08f4a823, + 0x852270a2, 0x64e27402, 0x69a26942, 0x61456a02, + 0x71798082, 0xe84af022, 0xf406e44e, 0x7938ec26, + 0x892e87aa, 0x89b26304, 0xf8070513, 0xf8048493, + 0x07078413, 0x08050793, 0x00879463, 0xa8394501, + 0x00090a63, 0x8763611c, 0x60dc0127, 0x84938526, + 0xb7cdf807, 0xf0ef85ce, 0xd965ec5f, 0x740270a2, + 0x694264e2, 0x614569a2, 0x11018082, 0xec06e822, + 0x7508842a, 0x860a468d, 0x0002f597, 0x73858593, + 0x488000ef, 0x8522e911, 0x800ff0ef, 0xc11c4782, + 0xc51c4792, 0xc15c47a2, 0xf0ef8522, 0x60e2eb2f, + 0x61056442, 0x715d8082, 0xf84ae0a2, 0xe486f44e, + 0xf052fc26, 0xe85aec56, 0x653ce45e, 0x458189ae, + 0x842a679c, 0x63848932, 0x867ff0ef, 0x09042783, + 0x0693862a, 0x8b850200, 0x0693c399, 0x601c02b0, + 0x451785a6, 0x05130003, 0x63980265, 0x4a1784ce, + 0x0a130003, 0x40ef05aa, 0x4a977e02, 0x8a930003, + 0x4b17046a, 0x0b130003, 0x4b97036b, 0x8b930003, + 0xd063026b, 0x640c0404, 0x0002d517, 0xe6850513, + 0x0019191b, 0x7b2240ef, 0x29857824, 0x07040413, + 0xf8048493, 0x08048793, 0x02f41c63, 0x640660a6, + 0x85a64601, 0xb0ef8522, 0x86aa54f1, 0x85d2864e, + 0xa0ef855a, 0x8b9b4852, 0x86520019, 0x852285a6, + 0xa95ff0ef, 0x85a689de, 0x8522864a, 0x7601b0ef, + 0xbb7d84aa, 0x854e75a2, 0x45f2a0ef, 0x85d2bd69, + 0xa0ef854e, 0xb5e14552, 0x651785ee, 0x05130003, + 0x83635765, 0x855a000a, 0x43f2a0ef, 0x854e85d2, + 0x4372a0ef, 0xb7192a85, 0x856685ee, 0x000a8363, + 0xa0ef855a, 0x85d24252, 0xa0ef854e, 0x2a8541d2, + 0x9863bf25, 0x86560147, 0xe42e8522, 0x99fff0ef, + 0x865e65a2, 0xb0ef8522, 0x85aa6f61, 0x4158b799, + 0x00ff0637, 0x0187569b, 0x0187179b, 0x169b8fd5, + 0x8ef10087, 0x66c18fd5, 0xf0068693, 0x0087571b, + 0x8fd98f75, 0x93811782, 0x8082953e, 0xec4e7139, + 0x89aae852, 0x85328a2e, 0x00034597, 0xac058593, + 0xf04af426, 0xfc06e456, 0x8ab2f822, 0x84ba8936, + 0x00f290ef, 0x66c1e539, 0x85ce8652, 0x80ef842a, + 0x571b0132, 0x179b0185, 0x8fd90185, 0x00ff06b7, + 0x0085171b, 0x8fd98f75, 0x551b6741, 0x07130085, + 0x8d79f007, 0x20238d5d, 0x479100a9, 0x70e2c09c, + 0x74428522, 0x790274a2, 0x6a4269e2, 0x61216aa2, + 0xe5978082, 0x85930003, 0x855657e5, 0x7b2290ef, + 0xe909842a, 0x864a66c1, 0x854e85d2, 0x37d200ef, + 0xb7e947d1, 0x0003e597, 0x56458593, 0x90ef8556, + 0x842a7902, 0x66c1e911, 0x85d2864a, 0x40ef854e, + 0x07936302, 0xb75d0200, 0x00030597, 0x5b058593, + 0x90ef8556, 0x842a76c2, 0x66c1e909, 0x85d2864a, + 0xf0ef854e, 0x47c112c1, 0x547db751, 0x7131b749, + 0xf526f922, 0xed4ef14a, 0xe556e952, 0xfcdee15a, + 0xf4e6f8e2, 0xeceef0ea, 0xfd068936, 0x89ae84aa, + 0xb0ef8a32, 0x842a64e1, 0x00036b17, 0x168b0b13, + 0x02010b93, 0x00033c17, 0xb64c0c13, 0x03010a93, + 0x01c10c93, 0x02810d13, 0x01810d93, 0x5e632901, + 0x57e10004, 0x00f40663, 0x450557d5, 0x0ef41563, + 0x00036917, 0x1b090913, 0x4601a855, 0x852685a2, + 0x3351b0ef, 0x855ae42a, 0x740290ef, 0x862a67a2, + 0x853e85da, 0x6ea290ef, 0x865ee921, 0x852685a2, + 0xe5aff0ef, 0x0e051763, 0x85627582, 0x24b2a0ef, + 0x661786d6, 0x06130003, 0x85a22166, 0xb0ef8526, + 0xc90d75b1, 0x47915742, 0x02f71663, 0xc39d411c, + 0x00036517, 0x20850513, 0x21f2a0ef, 0x00036517, + 0x20c50513, 0xdf3fc0ef, 0x852685a2, 0x5b41b0ef, + 0xb7b5842a, 0x866a86e6, 0x852685a2, 0xe26ff0ef, + 0x7602e541, 0x86d6876e, 0x855285ca, 0xe21ff0ef, + 0x47e2e53d, 0x1f634672, 0x75a204f6, 0x90ef8556, + 0xdd4d0172, 0x00036917, 0x15c90913, 0x460185a2, + 0xb0ef8526, 0x842a2831, 0x85ce4601, 0xb0ef8526, + 0x86aa2771, 0x85ca8622, 0x00036517, 0x1a850513, + 0x1a72a0ef, 0x70ea4501, 0x74aa744a, 0x69ea790a, + 0x6aaa6a4a, 0x7be66b0a, 0x7ca67c46, 0x6de67d06, + 0x80826129, 0x00036917, 0x11c90913, 0x6917bf45, + 0x09130003, 0xb75d12a9, 0x00036917, 0x0d890913, + 0x6917bf71, 0x09130003, 0xbf490ae9, 0x00347179, + 0xf022860a, 0xf406ec26, 0x842ae84a, 0xf0ef84ae, + 0xcd1dcbef, 0x45814601, 0xb0ef8522, 0x892a1fb1, + 0x85a64601, 0xb0ef8522, 0x86aa1ef1, 0x6597864a, + 0x85930003, 0x6517ffa5, 0x05130003, 0xa0ef0125, + 0x45011192, 0x740270a2, 0x694264e2, 0x80826145, + 0x660266a2, 0x852285a6, 0xe17ff0ef, 0x715db7e5, + 0x00037597, 0xe5858593, 0xe486fc26, 0xf84ae0a2, + 0xf052f44e, 0xe85aec56, 0xc0ef84aa, 0x5a6301c1, + 0xc0ef0205, 0x862a3421, 0x00037597, 0xe3058593, + 0x00036517, 0x11050513, 0x0bf2a0ef, 0x60a64501, + 0x74e26406, 0x79a27942, 0x6ae27a02, 0x61616b42, + 0x842a8082, 0x651785a6, 0x05130003, 0xa0efa325 }; #ifdef INIT_PATTERN_ZERO diff --git a/common/nwc/mss_io_config.h b/common/nwc/mss_io_config.h index 6049b0c..0875ffc 100644 --- a/common/nwc/mss_io_config.h +++ b/common/nwc/mss_io_config.h @@ -441,29 +441,29 @@ uint8_t mss_is_alternate_io_setting_sd(void); @code - case SD_MSSIO_CONFIGURATION: - if (mss_is_alternate_io_setting_sd() == true) - { - io_mux_and_bank_config_alt(); - } - else - { - io_mux_and_bank_config(); - } - switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); - break; - - case EMMC_MSSIO_CONFIGURATION: - if (mss_is_alternate_io_setting_emmc() == true) - { - io_mux_and_bank_config_alt(); - } - else - { - io_mux_and_bank_config(); - } - switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); - break; + case SD_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_sd() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); + break; + + case EMMC_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_emmc() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); + break; @endcode diff --git a/common/nwc/mss_scb_nwc_regs.h b/common/nwc/mss_scb_nwc_regs.h index b121a09..e3ee556 100644 --- a/common/nwc/mss_scb_nwc_regs.h +++ b/common/nwc/mss_scb_nwc_regs.h @@ -41,7 +41,7 @@ typedef struct __IO uint32_t PLL_CTRL2; /*!< Offset: 0x18 */ __IO uint32_t PLL_CAL; /*!< Offset: 0x1c */ __IO uint32_t PLL_PHADJ; /*!< Offset: 0x20 */ - __IO uint32_t SSCG_REG_0; /*!< Offset: 0x24 */ + __IO uint32_t SSCG_REG_0; /*!< Offset: 0x24 */ __IO uint32_t SSCG_REG_1; /*!< Offset: 0x28 */ __IO uint32_t SSCG_REG_2; /*!< Offset: 0x2c */ __IO uint32_t SSCG_REG_3; /*!< Offset: 0x30 */ @@ -52,24 +52,24 @@ typedef struct typedef struct { __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */ - __IO uint32_t BCLKMUX; /*!< Offset: 0x4 */ - __IO uint32_t PLL_CKMUX; /*!< Offset: 0x8 */ - __IO uint32_t MSSCLKMUX; /*!< Offset: 0xc */ - __IO uint32_t SPARE0; /*!< Offset: 0x10 */ - __IO uint32_t FMETER_ADDR; /*!< Offset: 0x14 */ - __IO uint32_t FMETER_DATAW; /*!< Offset: 0x18 */ + __IO uint32_t BCLKMUX; /*!< Offset: 0x4 */ + __IO uint32_t PLL_CKMUX; /*!< Offset: 0x8 */ + __IO uint32_t MSSCLKMUX; /*!< Offset: 0xc */ + __IO uint32_t SPARE0; /*!< Offset: 0x10 */ + __IO uint32_t FMETER_ADDR; /*!< Offset: 0x14 */ + __IO uint32_t FMETER_DATAW; /*!< Offset: 0x18 */ __IO uint32_t FMETER_DATAR; /*!< Offset: 0x1c */ - __IO uint32_t TEST_CTRL; /*!< Offset: 0x20 */ + __IO uint32_t TEST_CTRL; /*!< Offset: 0x20 */ } IOSCB_CFM_MSS; typedef struct { __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */ - __IO uint32_t RFCKMUX; /*!< Offset: 0x4 */ - __IO uint32_t SGMII_CLKMUX; /*!< Offset: 0x8 */ - __IO uint32_t SPARE0; /*!< Offset: 0xc */ - __IO uint32_t CLK_XCVR; /*!< Offset: 0x10 */ - __IO uint32_t TEST_CTRL; /*!< Offset: 0x14 */ + __IO uint32_t RFCKMUX; /*!< Offset: 0x4 */ + __IO uint32_t SGMII_CLKMUX; /*!< Offset: 0x8 */ + __IO uint32_t SPARE0; /*!< Offset: 0xc */ + __IO uint32_t CLK_XCVR; /*!< Offset: 0x10 */ + __IO uint32_t TEST_CTRL; /*!< Offset: 0x14 */ } IOSCB_CFM_SGMII; @@ -86,15 +86,15 @@ typedef struct } IOSCB_IO_CALIB_STRUCT; -#define MSS_SCB_MSS_PLL_BASE (0x3E001000U) /*!< ( MSS_SCB_MSS_PLL_BASE ) Base Address */ -#define MSS_SCB_DDR_PLL_BASE (0x3E010000U) /*!< ( MSS_SCB_DDR_PLL_BASE ) Base Address */ -#define MSS_SCB_SGMII_PLL_BASE (0x3E080000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ +#define MSS_SCB_MSS_PLL_BASE (0x3E001000U) /*!< ( MSS_SCB_MSS_PLL_BASE ) Base Address */ +#define MSS_SCB_DDR_PLL_BASE (0x3E010000U) /*!< ( MSS_SCB_DDR_PLL_BASE ) Base Address */ +#define MSS_SCB_SGMII_PLL_BASE (0x3E080000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ -#define MSS_SCB_MSS_MUX_BASE (0x3E002000U) /*!< ( MSS_SCB_MSS_MUX_BASE ) Base Address */ -#define MSS_SCB_SGMII_MUX_BASE (0x3E200000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ +#define MSS_SCB_MSS_MUX_BASE (0x3E002000U) /*!< ( MSS_SCB_MSS_MUX_BASE ) Base Address */ +#define MSS_SCB_SGMII_MUX_BASE (0x3E200000U) /*!< ( MSS_SCB_SGMII_PLL_BASE ) Base Address */ -#define IOSCB_IO_CALIB_SGMII_BASE (0x3E800000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ -#define IOSCB_IO_CALIB_DDR_BASE (0x3E040000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ +#define IOSCB_IO_CALIB_SGMII_BASE (0x3E800000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ +#define IOSCB_IO_CALIB_DDR_BASE (0x3E040000U) /*!< ( IOSCB_IO_CALIB_SGMII_BASE ) Base Address */ extern PLL_TypeDef * const MSS_SCB_MSS_PLL; diff --git a/mpfs_hal_version.h b/mpfs_hal_version.h index 4739d76..eb258d0 100644 --- a/mpfs_hal_version.h +++ b/mpfs_hal_version.h @@ -17,8 +17,8 @@ extern "C" { #endif #define MPFS_HAL_VERSION_MAJOR 2 -#define MPFS_HAL_VERSION_MINOR 2 -#define MPFS_HAL_VERSION_PATCH 107 +#define MPFS_HAL_VERSION_MINOR 3 +#define MPFS_HAL_VERSION_PATCH 100 #ifdef __cplusplus } diff --git a/startup_gcc/mss_entry.S b/startup_gcc/mss_entry.S index 47f2417..11f8566 100644 --- a/startup_gcc/mss_entry.S +++ b/startup_gcc/mss_entry.S @@ -92,20 +92,7 @@ _start: li x30,0 li x31,0 - # enable FPU and accelerator if present, setting ignored on E51 - li t0, MSTATUS_FS | MSTATUS_XS - csrs mstatus, t0 - - # Init floating point control register to zero - # skip if e51 - csrr a0, mhartid - beqz a0, .no_float -#ifdef __riscv_flen - fscsr x0 -#endif -.no_float: - - # make sure XLEN agrees with compilation choice, if not will loop here + # make sure XLEN agrees with compilation choice, if not will loop here .LxlenCheck: csrr t0, misa #if __riscv_xlen == 64 @@ -292,20 +279,7 @@ _start_non_bootloader_amp_image: bne a4, a5, 1b /* assume ints in init state */ /* assume PMP's set as required */ - # enable FPU and accelerator if present, setting ignored on E51 - li t0, MSTATUS_FS | MSTATUS_XS - csrs mstatus, t0 - - # Init floating point control register to zero - # skip if e51 - csrr a0, mhartid - beqz a0, .no_float -#ifdef __riscv_flen - fscsr x0 -#endif -.no_float: - - # make sure XLEN agrees with compilation choice, if not will loop here + # make sure XLEN agrees with compilation choice, if not will loop here .LxlenCheck: csrr t0, misa #if __riscv_xlen == 64 diff --git a/startup_gcc/mss_utils.S b/startup_gcc/mss_utils.S index e322022..5c58967 100644 --- a/startup_gcc/mss_utils.S +++ b/startup_gcc/mss_utils.S @@ -11,6 +11,8 @@ .section .text.init,"ax", %progbits .align 3 + +#include "../common/encoding.h" /*********************************************************************************** * @@ -44,7 +46,7 @@ pdma_transfer: fence ret -/*********************************************************************************** +/******************************************************************************* * * pdma_transfer_complete * Loops until transfer complete @@ -66,7 +68,7 @@ pdma_transfer_complete: ret - /*********************************************************************************** + /****************************************************************************** * * memfill() - fills memory, alternate to lib function when not available */ @@ -88,10 +90,10 @@ memfill: 2: ret -/*********************************************************************************** +/******************************************************************************* * - * The following config_copy() symbol overrides the weak symbol in the HAL and does - * a safe copy of HW config data + * The following config_copy() symbol overrides the weak symbol in the HAL and + * does a safe copy of HW config data */ // config_copy helper function: // a0 = dest @@ -112,9 +114,10 @@ config_copy: 2: ret - /*********************************************************************************** + /****************************************************************************** * - * config_16_copy () Copies a word at a time, used when copying to contigous registers + * config_16_copy () Copies a word at a time, used when copying to contigous + * registers */ // config_16_copy helper function: // a0 = dest @@ -135,9 +138,10 @@ config_16_copy: 2: ret -/*********************************************************************************** +/******************************************************************************* * - * config_32_copy () Copies a word at a time, used when copying to contigous registers + * config_32_copy () Copies a word at a time, used when copying to contiguous + * registers */ // config_copy helper function: // a0 = dest @@ -158,9 +162,10 @@ config_32_copy: 2: ret - /*********************************************************************************** + /****************************************************************************** * - * config_64_copy - copying using 64 bit loads, addresses must be on 64 bit boundary + * config_64_copy - copying using 64 bit loads, addresses must be on 64 bit + * boundary */ // config_64_copy helper function: // a0 = dest @@ -181,7 +186,7 @@ config_64_copy: 2: ret - /*********************************************************************************** + /****************************************************************************** * * fill_cache_new_seg_address and flush */ @@ -228,32 +233,46 @@ fill_cache_new_seg_address: .early_exit: ret -/*********************************************************************************** + /****************************************************************************** * - * clear_64_mem - clear memory using 64 bit writes, addresses must be on 64 bit - * boundary - * - * Note: This function is useful for initializing LIM as 64 bit writes are - * required to initialize ECC. The MPFS HAL does initialize all LIM on boot from - * eNVM, but when debugging bare metal projects from LIM, only the memory associated - * with the footprint of the program is initialised. So when debugging, if LIM memory - * outside the program itself is accessed, it must be initialized if it has not been - * initialized previously by a bootloader. + * turn_on_fpu() * - * clear_64_mem helper function: - * a0 = start address - * a1 = end address + * We only turn on floating point unit if required to save power * + * a0 = HARTS_TO_ENABLE_PPU, 0 => hart 0, 1 => hart1 etc */ - .globl clear_64_mem - .type clear_64_mem @function - clear_64_mem: - mv t1, a0 # start address to clear - mv t2, a1 # end address to clear + .globl turn_on_fpu + .type turn_on_fpu, @function +turn_on_fpu: + mv t1,a0 + csrr t2, mhartid + la t4, 1 + sll t4,t4,t2 + and t4,t4,t2 + beqz t4,1f + # enable FPU and accelerator if present, setting ignored on E51 + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 + # Init floating point control register to zero + # skip if e51 + beqz t2, 1f +#ifdef __riscv_flen + fscsr x0 +#endif 1: - sd x0, 0(t1) - add t1, t1, __SIZEOF_POINTER__ - blt t1, t2, 1b -.done_clear: ret + /****************************************************************************** + * + * turn_off_fpu() + * + * We can turn off if not using to save power + * + */ + .globl turn_off_fpu + .type turn_off_fpu, @function +turn_off_fpu: + # enable FPU and accelerator if present, setting ignored on E51 + li t0, MSTATUS_FS | MSTATUS_XS + csrc mstatus, t0 + ret diff --git a/startup_gcc/newlib_stubs.c b/startup_gcc/newlib_stubs.c index 2f47a4c..90ff6ea 100644 --- a/startup_gcc/newlib_stubs.c +++ b/startup_gcc/newlib_stubs.c @@ -222,6 +222,31 @@ int _write_r( void * reent, int file, char * ptr, int len ) */ if(!g_stdio_uart_init_done) { + mss_peripherals peripheral = MSS_PERIPH_INVALID; + + if ((&g_mss_uart0_lo == gp_my_uart) || (&g_mss_uart0_hi == gp_my_uart)) + { + peripheral = MSS_PERIPH_MMUART0; + } + else if ((&g_mss_uart1_lo == gp_my_uart) || (&g_mss_uart1_hi == gp_my_uart)) + { + peripheral = MSS_PERIPH_MMUART1; + } + else if ((&g_mss_uart2_lo == gp_my_uart) || (&g_mss_uart2_hi == gp_my_uart)) + { + peripheral = MSS_PERIPH_MMUART2; + } + else if ((&g_mss_uart3_lo == gp_my_uart) || (&g_mss_uart3_hi == gp_my_uart)) + { + peripheral = MSS_PERIPH_MMUART3; + } + else + { + ASSERT(0); + } + + (void)mss_config_clk_rst(peripheral, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); + MSS_UART_init(gp_my_uart, MICROCHIP_STDIO_BAUD_RATE, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY); diff --git a/startup_gcc/system_startup.c b/startup_gcc/system_startup.c index 09c88ac..fc786d6 100644 --- a/startup_gcc/system_startup.c +++ b/startup_gcc/system_startup.c @@ -19,6 +19,10 @@ #include "system_startup_defs.h" +static uint32_t parked_harts = 0U; +void* __dso_handle = (void*) &__dso_handle; +static void init_global_constructors(void); + /*============================================================================== * This function is called by the lowest enabled hart (MPFS_HAL_FIRST_HART) in * the configuration file : @@ -70,6 +74,7 @@ __attribute__((weak)) int main_first_hart(HLS_DATA* hls) #ifdef MPFS_HAL_HW_CONFIG (void)mss_nwc_init(); (void)mss_nwc_init_ddr(); + init_global_constructors(); /* main hart init's the PLIC */ PLIC_init_on_reset(); @@ -154,7 +159,9 @@ __attribute__((weak)) int main_first_hart(HLS_DATA* hls) stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h0$); hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); hls->in_wfi_indicator = HLS_MAIN_HART_FIN_INIT; - + + /* Turn off peripheral RAM that is not being used */ + mss_turn_off_unused_ram_clks(); /* * Turn on fic interfaces by default. Drivers will turn on/off other MSS * peripherals as required. @@ -206,6 +213,7 @@ __attribute__((weak)) int main_first_hart_app(HLS_DATA* hls) ptrdiff_t stack_top; init_memory(); + init_global_constructors(); hls->my_hart_id = MPFS_HAL_FIRST_HART; hls->in_wfi_indicator = HLS_MAIN_HART_STARTED; @@ -312,7 +320,7 @@ __attribute__((weak)) int main_first_hart_app(HLS_DATA* hls) */ __attribute__((weak)) int main_other_hart(HLS_DATA* hls) { -#if (IMAGE_LOADED_BY_BOOTLOADER == 0) // This also means no hardware init is required +#if (IMAGE_LOADED_BY_BOOTLOADER == 0) extern char __app_stack_top_h0; extern char __app_stack_top_h1; extern char __app_stack_top_h2; @@ -325,7 +333,12 @@ __attribute__((weak)) int main_other_hart(HLS_DATA* hls) const uint64_t app_stack_top_h3 = (const uint64_t)&__app_stack_top_h3 - (HLS_DEBUG_AREA_SIZE); const uint64_t app_stack_top_h4 = (const uint64_t)&__app_stack_top_h4 - (HLS_DEBUG_AREA_SIZE); +#ifdef TURN_OFF_POWER_TO_PARKED_HARTS + turn_off_power_to_parked_harts_ram(); +#endif + #ifdef MPFS_HAL_HW_CONFIG + turn_on_fpu((uint32_t)LIBERO_SETTING_TURN_ON_FPU); #ifdef MPFS_HAL_SHARED_MEM_ENABLED /* * If we are a boot-loader, and shared memory enabled (MPFS_HAL_SHARED_MEM_ENABLED) @@ -461,6 +474,20 @@ void load_virtual_rom(void) } #endif /* MPFS_HAL_HW_CONFIG */ +/*============================================================================== + * Initialize the global constructor before using any C++ feature which depends + * on global constructors. + */ +static void init_global_constructors(void) +{ + void (**fun_ptr)(void) = (void (**)(void))&__init_array_start; + while (fun_ptr != (void (**)(void))&__init_array_end) + { + (*fun_ptr)(); + fun_ptr++; + } +} + /*============================================================================== * Put the hart executing this code into an infinite loop executing from the * SCB system register memory space. @@ -486,6 +513,7 @@ static void park_hart(void) */ __attribute__((weak)) void e51(void) { + parked_harts |= (1U << 0U); /* Put hart in safe infinite WFI loop. */ park_hart(); } @@ -499,6 +527,7 @@ __attribute__((weak)) void e51(void) */ __attribute__((weak)) void u54_1(void) { + parked_harts |= (1U << 1U); /* Put hart in safe infinite WFI loop. */ park_hart(); } @@ -513,6 +542,7 @@ __attribute__((weak)) void u54_1(void) */ __attribute__((weak)) void u54_2(void) { + parked_harts |= (1U << 2U); /* Put hart in safe infinite WFI loop. */ park_hart(); } @@ -526,6 +556,7 @@ __attribute__((weak)) void u54_2(void) */ __attribute__((weak)) void u54_3(void) { + parked_harts |= (1U << 3U); /* Put hart in safe infinite WFI loop. */ park_hart(); } @@ -539,8 +570,9 @@ __attribute__((weak)) void u54_3(void) */ __attribute__((weak)) void u54_4(void) { + parked_harts |= (1U << 4U); /* Put hart in safe infinite WFI loop. */ - park_hart(); + park_hart(); } /*----------------------------------------------------------------------------- @@ -602,4 +634,34 @@ __attribute__((weak)) uint8_t init_pmp(uint8_t hart_id) return (0U); } +/** + * turn_off_power_to_parked_harts(void) + * + * Turns off power to harts that have been parked. + * + */ +__attribute__((weak)) void turn_off_power_to_parked_harts_ram(void) +{ + uint32_t hart_id = MPFS_HAL_FIRST_HART; + + while( hart_id <= MPFS_HAL_LAST_HART) + { + if ((parked_harts & (1U << hart_id)) !=0) + { + SYSREG->RAM_SHUTDOWN_CR |= ((1U << 8U)<< hart_id); + } + hart_id++; + } +} + +/** + * turn_on_power_to_hart_ram(void) + * + * Turns on power to a hart that was previously turned off + * + */ +__attribute__((weak)) void turn_on_power_to_hart_ram(uint32_t hart_id) +{ + SYSREG->RAM_SHUTDOWN_CR &= ~((1U << 8U)<< hart_id); +} diff --git a/startup_gcc/system_startup.h b/startup_gcc/system_startup.h index fc12703..9cd1505 100644 --- a/startup_gcc/system_startup.h +++ b/startup_gcc/system_startup.h @@ -42,6 +42,10 @@ typedef enum WFI_SM_ #define SHARED_MEM_DEFAULT_STATUS 0x00000000UL #endif +#ifndef LIBERO_SETTING_TURN_ON_FPU +#define LIBERO_SETTING_TURN_ON_FPU 0x1EUL +#endif + typedef struct HLS_DATA_ { volatile uint32_t in_wfi_indicator; @@ -103,6 +107,9 @@ extern unsigned long __u54_3_itim_end; extern unsigned long __u54_4_itim_start; extern unsigned long __u54_4_itim_end; +extern unsigned long __init_array_start; +extern unsigned long __init_array_end; + #ifndef MPFS_HAL_HW_CONFIG extern unsigned long __uninit_bottom$; extern unsigned long __uninit_top$; @@ -129,7 +136,10 @@ char * config_copy(void *dest, const void * src, size_t len); char * config_16_copy(void *dest, const void * src, size_t len); char * config_32_copy(void *dest, const void * src, size_t len); char * config_64_copy(void *dest, const void * src, size_t len); -char * clear_64_mem(uint64_t *start_address, uint64_t *end_address); +void turn_off_fpu(void); +void turn_off_power_to_parked_harts_ram(void); +void turn_on_fpu(uint32_t enable_info); +void turn_on_power_to_hart_ram(uint32_t hart_id); void copy_section (