-
Notifications
You must be signed in to change notification settings - Fork 9
/
Copy pathraplcap-cpuid.h
127 lines (95 loc) · 3.48 KB
/
raplcap-cpuid.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
#ifndef _RAPLCAP_CPUID_H_
#define _RAPLCAP_CPUID_H_
#ifdef __cplusplus
extern "C" {
#endif
#pragma GCC visibility push(hidden)
#define CPUID_VENDOR_ID_GENUINE_INTEL "GenuineIntel"
/*
* See: Software Developer's Manual, Volume 4
* See: https://en.wikichip.org/wiki/intel/cpuid
*/
//----
// Sandy Bridge is the first to support RAPL
#define CPUID_MODEL_SANDYBRIDGE 0x2A
#define CPUID_MODEL_SANDYBRIDGE_X 0x2D
#define CPUID_MODEL_IVYBRIDGE 0x3A
#define CPUID_MODEL_IVYBRIDGE_X 0x3E
#define CPUID_MODEL_HASWELL 0x3C
#define CPUID_MODEL_HASWELL_X 0x3F
#define CPUID_MODEL_HASWELL_L 0x45
#define CPUID_MODEL_HASWELL_G 0x46
#define CPUID_MODEL_BROADWELL 0x3D
#define CPUID_MODEL_BROADWELL_G 0x47
#define CPUID_MODEL_BROADWELL_X 0x4F
#define CPUID_MODEL_BROADWELL_D 0x56
#define CPUID_MODEL_SKYLAKE_L 0x4E
#define CPUID_MODEL_SKYLAKE_X 0x55
#define CPUID_MODEL_SKYLAKE 0x5E
#define CPUID_MODEL_KABYLAKE_L 0x8E
#define CPUID_MODEL_KABYLAKE 0x9E
#define CPUID_MODEL_CANNONLAKE_L 0x66
#define CPUID_MODEL_ICELAKE 0x7D
#define CPUID_MODEL_ICELAKE_L 0x7E
#define CPUID_MODEL_ICELAKE_X 0x6A
#define CPUID_MODEL_ICELAKE_D 0x6C
#define CPUID_MODEL_COMETLAKE 0xA5
#define CPUID_MODEL_COMETLAKE_L 0xA6
#define CPUID_MODEL_TIGERLAKE_L 0x8C
#define CPUID_MODEL_TIGERLAKE 0x8D
#define CPUID_MODEL_ALDERLAKE 0x97
#define CPUID_MODEL_ALDERLAKE_L 0x9A
#define CPUID_MODEL_RAPTORLAKE 0xB7
#define CPUID_MODEL_RAPTORLAKE_P 0xBA
#define CPUID_MODEL_RAPTORLAKE_S 0xBF
#define CPUID_MODEL_METEORLAKE_L 0xAA
#define CPUID_MODEL_LUNARLAKE_M 0xBD
#define CPUID_MODEL_SAPPHIRERAPIDS_X 0x8F
#define CPUID_MODEL_EMERALDRAPIDS_X 0xCF
#define CPUID_MODEL_GRANITERAPIDS_X 0xAD
#define CPUID_MODEL_GRANITERAPIDS_D 0xAE
#define CPUID_MODEL_XEON_PHI_KNL 0x57
#define CPUID_MODEL_XEON_PHI_KNM 0x85
#define CPUID_MODEL_ATOM_SILVERMONT 0x37 // Bay Trail, Valleyview
#define CPUID_MODEL_ATOM_SILVERMONT_MID 0x4A // Merriefield
// "ATOM_SILVERMONT_D" not supported by Linux kernel powercap interface...
#define CPUID_MODEL_ATOM_SILVERMONT_D 0x4D // Avoton, Rangeley
#define CPUID_MODEL_ATOM_AIRMONT 0x4C // Cherry Trail, Braswell
#define CPUID_MODEL_ATOM_AIRMONT_MID 0x5A // Moorefield
// "SoFIA" does not appear to have Linux kernel support
#define CPUID_MODEL_ATOM_SOFIA 0x5D
#define CPUID_MODEL_ATOM_GOLDMONT 0x5C // Apollo Lake
#define CPUID_MODEL_ATOM_GOLDMONT_D 0x5F // Denverton
#define CPUID_MODEL_ATOM_GOLDMONT_PLUS 0x7A // Gemini Lake
#define CPUID_MODEL_ATOM_TREMONT_D 0x86 // Jacobsville
#define CPUID_MODEL_ATOM_TREMONT 0x96 // Elkhart Lake
#define CPUID_MODEL_ATOM_TREMONT_L 0x9C // Jasper Lake
#define CPUID_MODEL_ATOM_CRESTMONT_X 0xAF // Sierra Forest
//----
/**
* Check that the CPU vendor is GenuineIntel.
*
* @return 1 if Intel, 0 otherwise
*/
int cpuid_is_vendor_intel(void);
/**
* Get the CPU family and model.
* Model parsing assumes that family=6.
*
* @param family not NULL
* @param model not NULL
*/
void cpuid_get_family_model(uint32_t* family, uint32_t* model);
/**
* Check that family=6 and model is one of those listed above.
*
* @param family
* @param model
* @return 1 if supported, 0 otherwise
*/
int cpuid_is_cpu_supported(uint32_t family, uint32_t model);
#pragma GCC visibility pop
#ifdef __cplusplus
}
#endif
#endif