osctest_sv.config

# $Id: osctest_sv.config,v 1.1 2002/06/27 18:27:00 dwchin Exp $
#
# Test the bit-wise logic conditions with the state vector
#
H1:SV_Operator_Go       bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x01 fraction=1.
#H1:SV_Conlog_NoChange   bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x02 fraction=1.
H1:SV_PSL_OK            bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x04 fraction=1.
#H1:SV_CommonMode        bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x08 fraction=1.
#H1:SV_ISC               bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x10 fraction=1.
#H1:SV_AutoLocked        bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x20 fraction=1.
#H1:SV_NoExcitation      bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x40 fraction=1.
#H1:SV_DAQ_OK            bitand  "H1:IFO-SV_STATE_VECTOR" mask=0x80 fraction=1.
#H1:SV_AllOnSkipExc      bitand  "H1:IFO-SV_STATE_VECTOR" mask=0xBF fraction=1.
#H1:SV_AllBitsOn         bitand  "H1:IFO-SV_STATE_VECTOR" mask=0xFF fraction=1.