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Virtual Memory SV-32 Address Translation Scheme Tests and Covergroups (…
…#516) * SV32 Tests and Covergroups added * macro file updated and header_file added * RVMODEL_HALT label added * Update test.yml Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> * Update test.yml Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> * alignment added for 4KB page boundry * model_test.h updated * removed hardware update tests and added its covergroups in a single file * model_test updated * increase the size limit to 10GB * Update Coverpoints to use translator -> optimized and more readable * Move the Virtual Memory SV-32 Tests to follow directory structure * Move the PMP Covergroups to follow directory structure * Move the PMP Covergroups to follow directory structure * Covergroup for MPRV test added * MPRV test for S and U mode added * tvm, satp, rsw tests added * Updated the test to dump the correct value for walking ones * tests and covergroups for the combination of mprv and sum bit added * Update Comments in the coverage file Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> --------- Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> Co-authored-by: Umer Shahid <umer.shahid@10xengineers.ai> Co-authored-by: James Shi <shiqinghao.sqh@alibaba-inc.com>
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riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S
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| // ---------------------------------------------------------------------------------------------------------------------- | ||
| // This test is part of the test plan for the SV-32-based Virtual Memory System, available at: | ||
| // https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 | ||
| // Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid | ||
| // ---------------------------------------------------------------------------------------------------------------------- | ||
| // Copyright (c) 2020. RISC-V International. All rights reserved. | ||
| // SPDX-License-Identifier: BSD-3-Clause | ||
| // ---------------------------------------------------------------------------------------------------------------------- | ||
| // Test Explanation: | ||
| // RISC-V Privileged Architecture ISA Manual -- Section 10.3 | ||
| // | ||
| // Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. | ||
| // Future updates will align with ISA version 1.13. | ||
| // | ||
| // This test verifies the functionality of mstatus.TVM bit with the satp and sfence.vma | ||
| // Test cases are as follows: | ||
| // ---------------------------------------------------------------------------------------------------------------------- | ||
| // 1. satp and sfence.vma accessed in M Mode with mstatus.tvm bit set -> Successful | ||
| // 2. satp and sfence.vma accessed in S Mode with mstatus.tvm bit set -> illegal instruction exception | ||
| // | ||
| // Total Expected Faults: 2 | ||
| // ---------------------------------------------------------------------------------------------------------------------- | ||
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| //TODO: instead of using two different tests, use a single test for hart/software update. | ||
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| #include "model_test.h" | ||
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| #include "arch_test.h" | ||
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| RVTEST_ISA("RV32I_Zicsr") | ||
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| # Test code region | ||
| .section .text.init | ||
| .globl rvtest_entry_point | ||
| rvtest_entry_point: | ||
| RVMODEL_BOOT | ||
| RVTEST_CODE_BEGIN | ||
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| #ifdef TEST_CASE_1 | ||
| RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm) | ||
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| RVTEST_SIGBASE( x13,signature_x13_1) | ||
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| main: | ||
| #ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine | ||
| LI a4, 0xceed | ||
| RVTEST_SIGUPD(x13,a4) | ||
| #endif | ||
| #ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine | ||
| LI a4, 0xbeed | ||
| RVTEST_SIGUPD(x13,a4) | ||
| #endif | ||
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| ALL_MEM_PMP // set the PMP permissions for the whole memory | ||
| csrw satp, zero // write satp with all zeros (bare mode) | ||
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| #set the mstatus with the TVM bit | ||
| LI (t4, MSTATUS_TVM) | ||
| csrw mstatus, t4 | ||
| csrr t3, mstatus | ||
| RVTEST_SIGUPD(x13,t3) | ||
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| // ------------------------------------------------------------------------------------------------------------ | ||
| // satp access in M Mode using csrrw, csrrc, csrrs | ||
| // ------------------------------------------------------------------------------------------------------------ | ||
| li t0, 1 //initial value for t0 = 1 | ||
| #successful access | ||
| csrw satp, t0 // write satp with some value | ||
| csrr t3, satp | ||
| RVTEST_SIGUPD(x13,t3) | ||
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| #successful access | ||
| sfence.vma | ||
| nop | ||
| nop | ||
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| // ------------------------------------------------------------------------------------------------------------ | ||
| // satp access in S Mode | ||
| // ------------------------------------------------------------------------------------------------------------ | ||
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| RVTEST_GOTO_LOWER_MODE Smode | ||
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| li t0, 1 //initial value for t0 = 1 | ||
| csrw satp, t0 // write satp with some value | ||
| nop | ||
| nop | ||
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| sfence.vma | ||
| nop | ||
| nop | ||
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| RVTEST_GOTO_MMODE // Switching back to M mode | ||
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| #endif | ||
| //--------------------------------------------------------------------------------------------------------------------------------- | ||
| RVTEST_CODE_END | ||
| RVMODEL_HALT | ||
| RVTEST_DATA_BEGIN | ||
| .align 22 | ||
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| //--------------------------------------------------------------------------------------------------------------------------------- | ||
| //--------------------------------------------------------------------------------------------------------------------------------- | ||
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| #ifdef rvtest_strap_routine | ||
| .align 12 //complete the 4KB permission memory range | ||
| rvtest_slvl1_pg_tbl: | ||
| RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) | ||
| #endif | ||
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| RVTEST_DATA_END | ||
| .align 12 | ||
| RVMODEL_DATA_BEGIN | ||
| rvtest_sig_begin: | ||
| sig_begin_canary: | ||
| CANARY; | ||
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| // test signatures initialization | ||
| signature_x13_1: | ||
| .fill 64*(XLEN/32),4,0xcafebeef | ||
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| // trap signatures initialization | ||
| #ifdef rvtest_mtrap_routine | ||
| mtrap_sigptr: | ||
| .fill 64*(XLEN/32),4,0xdeadbeef | ||
| #endif | ||
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| sig_end_canary: | ||
| CANARY; | ||
| rvtest_sig_end: | ||
| RVMODEL_DATA_END |
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