diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
index 72f4a1d9c..3d9efe618 100644
--- a/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
+++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
@@ -4,13 +4,12 @@
 //
 // This assembly file tests the fli.d instruction
 // for the following ISA configurations:
-// * RV32ID_Zfa
 // * RV64ID_Zfa
 
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV32ID_Zfa,RV64ID_Zfa")
+RVTEST_ISA("RV64ID_Zfa")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -22,7 +21,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fli.d)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fli.d)
 
 // Registers with a special purpose
 #define SIG_BASEREG x1
diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
index 4e7a6f83e..9ee6d345a 100644
--- a/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
+++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
@@ -4,13 +4,12 @@
 //
 // This assembly file tests the fli.s instruction
 // for the following ISA configurations:
-// * RV32IF_Zfa
 // * RV64IF_Zfa
 
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV32IF_Zfa,RV64IF_Zfa")
+RVTEST_ISA("RV64IF_Zfa")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -22,7 +21,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fli.s)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fli.s)
 
 // Registers with a special purpose
 #define SIG_BASEREG x1