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Added Zfinx and Zfh tests #367

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merged 6 commits into from
Mar 26, 2024
Merged

Added Zfinx and Zfh tests #367

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42e5c7b
Updated Zfinx and Zfh test suites
anuani21 Jul 3, 2023
e9d6c30
Zfh FMA Test
anuani21 Feb 6, 2024
8f442d6
Zfinx FMA Tests
anuani21 Feb 6, 2024
3a38764
Zfh Model-15 FMA tests
anuani21 Feb 7, 2024
50fa12a
Updated convert instructions
anuani21 Mar 25, 2024
d4c4da7
Updated CHANGELOG.md
anuani21 Mar 26, 2024
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4 changes: 4 additions & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
@@ -1,4 +1,8 @@
# CHANGELOG
## [3.8.11] - 2024-03-26
- Added test suites for Zfh extensions.
- Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions.
- Added test suites for Zfinx extensions.

## [3.6.8] - 2023-06-22
- Fix broken hyperlink in README
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21 changes: 20 additions & 1 deletion riscv-test-suite/env/arch_test.h
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Expand Up @@ -216,12 +216,31 @@
#define FLREG fld
#define FSREG fsd
#define FREGWIDTH 8
#elif FLEN==16
#define FLREG flh
#define FSREG fsh
#define FREGWIDTH 2
#else
#define FLREG flq
#define FSREG fsq
#define FREGWIDTH 16
#endif

#if ZFINX==1
#define FLREG ld
#define FSREG sd
#define FREGWIDTH 8
#define FLEN 64
#if XLEN==64
#define SIGALIGN 8
#else
#define SIGALIGN 4
#endif
#elif ZDINX==1
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This looks wrong; ZFinx only needs 4B registers, NOT 8B registers. And, if both Zfinx and Zdinx exist, then you need to accommodate both sizes, don't you? And, they're different on RV64 vs. RV32. So Zdinx would need to execute 2 separate LW ops on an RV32 compared to a single LD that RV64 to replace a FLD.

#define FLREG LREG
#define FSREG SREG
#define FREGWIDTH 8
#define FLEN 64
#endif

#if SIGALIGN==8
#define CANARY \
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15 changes: 13 additions & 2 deletions riscv-test-suite/env/test_macros.h
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Expand Up @@ -4,18 +4,29 @@


#define NAN_BOXED(__val__,__width__,__max__) ;\
.if __width__ == 16 ;\
.hword __val__ ;\
.endif ;\
.if __width__ == 32 ;\
.word __val__ ;\
.else ;\
.dword __val__ ;\
.endif ;\
.if __max__ > __width__ ;\
.set pref_bytes,(__max__-__width__)/32 ;\
.if __width__ == 16 ;\
.set pref_bytes,(__max__-__width__)/16;\
.else ;\
.set pref_bytes,(__max__-__width__)/32;\
.endif ;\
.else ;\
.set pref_bytes, 0 ;\
.endif ;\
.rept pref_bytes ;\
.word 0xffffffff ;\
.if __width__ == 16 ;\
.hword 0xffff ;\
.else ;\
.word 0xffffffff ;\
.endif ;\
.endr ;

#define ZERO_EXTEND(__val__,__width__,__max__) ;\
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5,311 changes: 5,311 additions & 0 deletions riscv-test-suite/rv32i_m/Zfh/src/fadd_b1-01.S
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