From ea99406337b8001750008f37122cb31374c813f6 Mon Sep 17 00:00:00 2001 From: liweiwei Date: Mon, 20 Dec 2021 11:29:14 +0800 Subject: [PATCH 1/2] add support for cbo.zero --- coverage/rv32i_cbo.cgf | 14 ++++++++++++++ coverage/rv64i_cbo.cgf | 14 ++++++++++++++ riscv-ctg/CHANGELOG.md | 10 ++++++---- riscv-ctg/riscv_ctg/data/template.yaml | 19 ++++++++++++++++++- riscv-ctg/riscv_ctg/generator.py | 11 +++++++---- riscv-test-suite/env/arch_test.h | 2 +- 6 files changed, 60 insertions(+), 10 deletions(-) create mode 100644 coverage/rv32i_cbo.cgf create mode 100644 coverage/rv64i_cbo.cgf diff --git a/coverage/rv32i_cbo.cgf b/coverage/rv32i_cbo.cgf new file mode 100644 index 000000000..d1d3f4114 --- /dev/null +++ b/coverage/rv32i_cbo.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +cbozero: + config: + - check ISA:=regex(.*I.*Zicboz.*Zicsr.*) + mnemonics: + cbo.zero: 0 + rs1: + <<: *all_regs_mx0 + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 12, False)': 0 + 'walking_zeros("rs1_val", 12, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [12])': 0 diff --git a/coverage/rv64i_cbo.cgf b/coverage/rv64i_cbo.cgf new file mode 100644 index 000000000..7478394a9 --- /dev/null +++ b/coverage/rv64i_cbo.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +cbozero: + config: + - check ISA:=regex(.*I.*Zicboz.*Zicsr.*) + mnemonics: + cbo.zero: 0 + rs1: + <<: *all_regs_mx0 + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 12, False)': 0 + 'walking_zeros("rs1_val", 12, False)': 0 + 'uniform_random(10, 100, ["rs1_val"], [12])': 0 diff --git a/riscv-ctg/CHANGELOG.md b/riscv-ctg/CHANGELOG.md index 0371043af..58b63c087 100644 --- a/riscv-ctg/CHANGELOG.md +++ b/riscv-ctg/CHANGELOG.md @@ -2,11 +2,13 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). - Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [WIP-DEV] +- Added support for zicboz extexnsion + ## [0.12.2] - 2024-03-06 - Add Zfa support. (PR#60) - Initial covergroups for Zvk* instructions (PR#61) @@ -19,7 +21,7 @@ versioned header while the `WIP-DEV` is left empty - Add hardcoded register testcases to dataset.cgf and rv32im.cgf - Define rs1_val_data for c.ldsp in imc.yaml - Update "opcode" to "mnemonics" in the cgf files -- Delete main.yml +- Delete main.yml - Update test.yml for CI - Define rs1_val_data for instructions from zicfiss.cgf in template.yaml - Add "warning" in the verbose definition @@ -30,7 +32,7 @@ versioned header while the `WIP-DEV` is left empty - Add unratified Zaamo subcomponent of A extension - Add unratified B extension - Fix issues with csr_comb -- Minor fix in kslraw.u in rv32ip +- Minor fix in kslraw.u in rv32ip - Fix incorrect 'sig:' entry in aes32dsi in template.yaml - Add sig and sz for instructions in template.yaml - Minor change of rd definition in c.lui in rv32ec @@ -69,7 +71,7 @@ versioned header while the `WIP-DEV` is left empty ## [0.10.2] - 2022-10-20 - Fixed use of lowercase LI. -- Fixed correctval to ?? in comments. +- Fixed correctval to ?? in comments. - Fixed sw to SREG for K tests. - Added canaries and signature boundary labels. diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index 40d23c717..5c9b0624a 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -10415,7 +10415,24 @@ czero.nez: // $comment // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val - TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +cbo.zero: + std_op: + sig: + stride: 1 + sz: 'RVMODEL_CBZ_BLOCKSIZE' + xlen: [32,64] + isa: + - IZicbozZicsr + formattype: 'zformat' + rs1_op_data: *all_regs_mx0 + rs1_val_data: 'gen_usign_dataset(12)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op1val:$rs1_val + TEST_CBO_ZERO($swreg,$rs1,$inst,$rs1_val) amoadd.w: sig: diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 082e31126..a6014bf89 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -113,7 +113,8 @@ def get_rm(opcode): 'ppbrrformat': ['rs1', 'rs2', 'rd'], 'prrformat': ['rs1', 'rs2', 'rd'], 'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'], - 'dcasrformat': ['rs1', 'rs2', 'rd'] + 'dcasrformat': ['rs1', 'rs2', 'rd'], + 'zformat': ['rs1'] } ''' Dictionary mapping instruction formats to operands used by those formats ''' @@ -170,7 +171,8 @@ def get_rm(opcode): 'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)', 'prrformat': '["rs1_val", "rs2_val"]', 'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']", - 'dcasrformat': '["rs1_val", "rs2_val"]' + 'dcasrformat': '["rs1_val", "rs2_val"]', + 'zformat': ['rs1'] } ''' Dictionary mapping instruction formats to operand value variables used by those formats ''' @@ -1006,6 +1008,7 @@ def valreg(self,instr_dict): else: FLEN = 0 XLEN = max(self.opnode['xlen']) + RVMODEL_CBZ_BLOCKSIZE = XLEN SIGALIGN = max(XLEN,FLEN)/8 stride_sz = eval(suffix) template = Template(eval(self.opnode['val']['val_template'])) @@ -1318,7 +1321,7 @@ def reformat_instr(self, instr_dict): value = '0x' + value[2:].zfill(int(self.xlen/4)) value = struct.unpack(size, bytes.fromhex(value[2:]))[0] else: - value = int(value) + value = toint(value) # value = '0x' + struct.pack(size,value).hex() #print("test",hex(value)) instr_dict[i][field] = hex(value) @@ -1425,7 +1428,7 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): # dval = (instr['rs{0}_val'.format(i)],self.iflen) data.extend(instr['val_section']) if instr['swreg'] != sreg or eval(instr['offset'],{}, - {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8}) == 0: + {'FLEN':width,'XLEN':self.xlen,'RVMODEL_CBZ_BLOCKSIZE':self.xlen, 'SIGALIGN':max(self.xlen,self.flen)/8}) == 0: sign.append(signode_template.substitute( {'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz})) n = stride diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index 18ef0e801..129907aa5 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -159,7 +159,7 @@ #define INT_CAUSE_MSK ((1<<4)-1) #endif - // set defaults +// set defaults #ifndef NUM_SPECD_EXCPTCAUSES #define NUM_SPECD_EXCPTCAUSES 16 #define EXCPT_CAUSE_MSK ((1<<4)-1) From 3d1beb4153400fb01bd0dfe56e6f76e39391c080 Mon Sep 17 00:00:00 2001 From: trdthg Date: Thu, 19 Sep 2024 10:19:03 +0800 Subject: [PATCH 2/2] Add Zicbom and Zicbop extension --- coverage/cmo/cbom.cgf | 37 ++++++++ coverage/cmo/cbop.cgf | 37 ++++++++ coverage/{rv32i_cbo.cgf => cmo/cboz.cgf} | 2 +- coverage/cmo/rvi_cmo.cgf | 14 --- coverage/dataset.cgf | 33 +++++-- coverage/rv64i_cbo.cgf | 14 --- riscv-ctg/CHANGELOG.md | 2 +- riscv-ctg/riscv_ctg/data/template.yaml | 111 ++++++++++++++++++++++- riscv-ctg/riscv_ctg/generator.py | 3 +- riscv-test-suite/env/test_macros.h | 11 ++- 10 files changed, 219 insertions(+), 45 deletions(-) create mode 100644 coverage/cmo/cbom.cgf create mode 100644 coverage/cmo/cbop.cgf rename coverage/{rv32i_cbo.cgf => cmo/cboz.cgf} (97%) delete mode 100644 coverage/cmo/rvi_cmo.cgf delete mode 100644 coverage/rv64i_cbo.cgf diff --git a/coverage/cmo/cbom.cgf b/coverage/cmo/cbom.cgf new file mode 100644 index 000000000..ab649375f --- /dev/null +++ b/coverage/cmo/cbom.cgf @@ -0,0 +1,37 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +cbo.clean: + config: + - check ISA:=regex(.*I.*Zicbom.*Zicsr.*) + mnemonics: + cbo.clean: 0 + rs1: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn] + +cbo.flush: + config: + - check ISA:=regex(.*I.*Zicbom.*Zicsr.*) + mnemonics: + cbo.flush: 0 + rs1: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn] + +cbo.inval: + config: + - check ISA:=regex(.*I.*Zicbom.*Zicsr.*) + mnemonics: + cbo.inval: 0 + rs1: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn] diff --git a/coverage/cmo/cbop.cgf b/coverage/cmo/cbop.cgf new file mode 100644 index 000000000..a335549e3 --- /dev/null +++ b/coverage/cmo/cbop.cgf @@ -0,0 +1,37 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +prefetch.i: + config: + - check ISA:=regex(.*I.*Zicbop.*Zicsr.*) + mnemonics: + prefetch.i: 0 + rs1: + <<: *all_regs + val_comb: + <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5] + +prefetch.r: + config: + - check ISA:=regex(.*I.*Zicbop.*Zicsr.*) + mnemonics: + prefetch.r: 0 + rs1: + <<: *all_regs + val_comb: + <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5] + +prefetch.w: + config: + - check ISA:=regex(.*I.*Zicbop.*Zicsr.*) + mnemonics: + prefetch.w: 0 + rs1: + <<: *all_regs + val_comb: + <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5] diff --git a/coverage/rv32i_cbo.cgf b/coverage/cmo/cboz.cgf similarity index 97% rename from coverage/rv32i_cbo.cgf rename to coverage/cmo/cboz.cgf index d1d3f4114..3c953d4cc 100644 --- a/coverage/rv32i_cbo.cgf +++ b/coverage/cmo/cboz.cgf @@ -1,6 +1,6 @@ # For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore -cbozero: +cbo.zero: config: - check ISA:=regex(.*I.*Zicboz.*Zicsr.*) mnemonics: diff --git a/coverage/cmo/rvi_cmo.cgf b/coverage/cmo/rvi_cmo.cgf deleted file mode 100644 index 89318e156..000000000 --- a/coverage/cmo/rvi_cmo.cgf +++ /dev/null @@ -1,14 +0,0 @@ -# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore - -cbozero: - config: - - check ISA:=regex(.*I.*Zicboz.*Zicsr.*) - opcode: - cbo.zero: 0 - rs1: - <<: *all_regs_mx0 - val_comb: - abstract_comb: - 'walking_ones("rs1_val", 12, False)': 0 - 'walking_zeros("rs1_val", 12, False)': 0 - 'uniform_random(10, 100, ["rs1_val"], [12])': 0 diff --git a/coverage/dataset.cgf b/coverage/dataset.cgf index b84b69dd8..0ac4c38c5 100644 --- a/coverage/dataset.cgf +++ b/coverage/dataset.cgf @@ -305,7 +305,7 @@ datasets: r0fmt_op_comb: &r0fmt_op_comb 'rs1 == 0': 0 'rs1 != 0': 0 - + base_rs1val_sgn: &base_rs1val_sgn 'rs1_val == (-2**(xlen-1))': 0 'rs1_val == 0': 0 @@ -317,7 +317,7 @@ datasets: 'rs1_val == 0 and rs2_val == 0': 0 'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0 'rs1_val == 1 and rs2_val == 0': 0 - + base_rs2val_sgn: &base_rs2val_sgn 'rs2_val == (-2**(xlen-1))': 0 'rs2_val == 0': 0 @@ -330,12 +330,11 @@ datasets: 'rs3_val == (2**(xlen-1)-1)': 0 'rs3_val == 1': 0 - base_rs1val_unsgn: &base_rs1val_unsgn 'rs1_val == 0': 0 'rs1_val == (2**(xlen)-1)': 0 'rs1_val == 1': 0 - + base_rs2val_unsgn: &base_rs2val_unsgn 'rs2_val == 0': 0 'rs2_val == (2**(xlen)-1)': 0 @@ -356,7 +355,7 @@ datasets: div_corner_case: &div_corner_case 'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0 - + rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn 'rs1_val > 0 and rs2_val > 0': 0 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 @@ -374,12 +373,23 @@ datasets: 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 + zicbop_ifmt_val_comb_unsgn: &zicbop_ifmt_val_comb_unsgn + 'rs1_val == imm_val and rs1_val == 0': 0 + 'rs1_val < imm_val and rs1_val != 0': 0 + 'rs1_val > imm_val and imm_val == 0': 0 + ifmt_base_immval_sgn: &ifmt_base_immval_sgn 'imm_val == (-2**(12-1))': 0 'imm_val == 0': 0 'imm_val == (2**(12-1)-1)': 0 'imm_val == 1': 0 + ifmt_base_immval11_5_sgn: &ifmt_base_immval11_5_sgn + 'imm_val == (-2**(7-1)) << 5': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(7-1)-1) << 5': 0 + 'imm_val == 1<<5': 0 + ifmt_base_immval_sgn_len: &ifmt_base_immval_sgn_len 'imm_val == (-2**(ceil(log(xlen,2))-1))': 0 'imm_val == 0': 0 @@ -445,7 +455,7 @@ datasets: 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 - + bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn 'rs1_val > 0 and rs2_val > 0': 0 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 @@ -490,12 +500,17 @@ datasets: 'walking_ones("imm_val", 5, False)': 0 'walking_zeros("imm_val", 5, False)': 0 'alternate("imm_val", 5, False)': 0 - + + ifmt_immval_walking_11_5: &ifmt_immval_walking_11_5 + 'walking_ones("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0 + 'walking_zeros("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0 + 'alternate("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0 + rs1val_walking_unsgn: &rs1val_walking_unsgn 'walking_ones("rs1_val", xlen,False)': 0 'walking_zeros("rs1_val", xlen,False)': 0 'alternate("rs1_val",xlen,False)': 0 - + rs2val_walking_unsgn: &rs2val_walking_unsgn 'walking_ones("rs2_val", xlen,False)': 0 'walking_zeros("rs2_val", xlen,False)': 0 @@ -509,7 +524,7 @@ datasets: 'walking_ones("imm_val", 6)': 0 'walking_zeros("imm_val", 6)': 0 'alternate("imm_val",6)': 0 - + ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn 'walking_ones("imm_val", 12,False)': 0 'walking_zeros("imm_val", 12,False)': 0 diff --git a/coverage/rv64i_cbo.cgf b/coverage/rv64i_cbo.cgf deleted file mode 100644 index 7478394a9..000000000 --- a/coverage/rv64i_cbo.cgf +++ /dev/null @@ -1,14 +0,0 @@ -# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore - -cbozero: - config: - - check ISA:=regex(.*I.*Zicboz.*Zicsr.*) - mnemonics: - cbo.zero: 0 - rs1: - <<: *all_regs_mx0 - val_comb: - abstract_comb: - 'walking_ones("rs1_val", 12, False)': 0 - 'walking_zeros("rs1_val", 12, False)': 0 - 'uniform_random(10, 100, ["rs1_val"], [12])': 0 diff --git a/riscv-ctg/CHANGELOG.md b/riscv-ctg/CHANGELOG.md index 58b63c087..1394e93cf 100644 --- a/riscv-ctg/CHANGELOG.md +++ b/riscv-ctg/CHANGELOG.md @@ -7,7 +7,7 @@ Only when a release to the main branch is done, the contents of the WIP-DEV are versioned header while the `WIP-DEV` is left empty ## [WIP-DEV] -- Added support for zicboz extexnsion +- Added support for zicboz/zicbom/zicbop extexnsion ## [0.12.2] - 2024-03-06 - Add Zfa support. (PR#60) diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index 5c9b0624a..da4291168 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -10424,15 +10424,120 @@ cbo.zero: sz: 'RVMODEL_CBZ_BLOCKSIZE' xlen: [32,64] isa: - - IZicbozZicsr + - IZicboz_Zicsr formattype: 'zformat' rs1_op_data: *all_regs_mx0 - rs1_val_data: 'gen_usign_dataset(12)' + rs1_val_data: 'gen_usign_dataset(12) + gen_sp_dataset(xlen,False)' template: |- // $comment // opcode: $inst ; op1:$rs1; op1val:$rs1_val - TEST_CBO_ZERO($swreg,$rs1,$inst,$rs1_val) + TEST_CBO($swreg,$rs1,$inst,$rs1_val) + +cbo.clean: + std_op: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + isa: + - IZicbom_Zicsr + formattype: 'zformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op1val:$rs1_val + TEST_CBO($swreg,$rs1,$inst,$rs1_val) + +cbo.flush: + std_op: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + isa: + - IZicbom_Zicsr + formattype: 'zformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op1val:$rs1_val + TEST_CBO($swreg,$rs1,$inst,$rs1_val) + +cbo.inval: + std_op: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + isa: + - IZicbom_Zicsr + formattype: 'zformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op1val:$rs1_val + TEST_CBO($swreg,$rs1,$inst,$rs1_val) + +prefetch.i: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicbop_Zicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val + TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val) + +prefetch.r: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicbop_Zicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)' + imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val + TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val) + +prefetch.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicbop_Zicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)' + imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val + TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val) amoadd.w: sig: diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index a6014bf89..3d69c725f 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -172,7 +172,7 @@ def get_rm(opcode): 'prrformat': '["rs1_val", "rs2_val"]', 'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']", 'dcasrformat': '["rs1_val", "rs2_val"]', - 'zformat': ['rs1'] + 'zformat': "['rs1_val']" } ''' Dictionary mapping instruction formats to operand value variables used by those formats ''' @@ -1134,6 +1134,7 @@ def swreg(self, instr_dict): else: FLEN = 0 XLEN = max(self.opnode['xlen']) + RVMODEL_CBZ_BLOCKSIZE = XLEN SIGALIGN = max(XLEN,FLEN)/8 stride_sz = eval(suffix) for instr in instr_dict: diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 4ed2bc010..4f56e2151 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -769,14 +769,21 @@ nop ;\ csrr flagreg, fcsr ;\ RVTEST_SIGUPD_F(swreg,destreg,flagreg) -#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val) ;\ -LI(rs1,imm_val&(RVMODEL_CBZ_BLOCKSIZE-1)) ;\ +#define TEST_CBO(swreg,rs1,inst,rs1_val) ;\ +LI(rs1,rs1_val&(RVMODEL_CBZ_BLOCKSIZE-1)) ;\ add rs1,rs1,swreg ;\ inst (rs1) ;\ nop ;\ nop ;\ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE) +#define TEST_PREFETCH(swreg,rs1,inst,rs1_val,imm_val) ;\ +LI(rs1,rs1_val) ;\ +inst imm_val(rs1) ;\ +nop ;\ +nop ;\ +ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE) + #define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\ LI(TEMP_REG,VAL) ;\ and TEMP_REG,TEMP_REG,MASK_REG ;\