sys_regs: remove SXL and UXL accessors

The SXL and UXL accessor are not needed since RV32 will never use them.
Remove them to make the code cleaner.

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>

model/riscv_sys_regs.sail

@@ -210,18 +210,6 @@ function effectivePrivilege(t : AccessType(ext_access_type), m : Mstatus, priv :
   then privLevel_of_bits(m[MPP])
   else priv
 
-function get_mstatus_SXL(m : Mstatus) -> arch_xlen = {
-  if   xlen == 32
-  then architecture(RV32)
-  else m[SXL]
-}
-
-function get_mstatus_UXL(m : Mstatus) -> arch_xlen = {
-  if   xlen == 32
-  then architecture(RV32)
-  else m[UXL]
-}
-
 function get_mstatus_SD(m : Mstatus) -> bits(1) = {
   if   xlen == 32 then m[SD_32]
   else m[SD_64]
@@ -309,8 +297,8 @@ function cur_architecture() -> Architecture = {
     let a : arch_xlen =
       match cur_privilege {
         Machine    => misa[MXL],
-        Supervisor => get_mstatus_SXL(mstatus),
-        User       => get_mstatus_UXL(mstatus)
+        Supervisor => mstatus[SXL],
+        User       => mstatus[UXL],
       };
     architecture(a)
   }

model/riscv_vmem.sail

@@ -238,8 +238,7 @@ function translationMode(priv : Privilege) -> SATPMode = {
     }
   else if xlen == 64 then {
     // Translation mode is based on mstatus.SXL, which could be RV32 when xlen==64
-    let arch = architecture(get_mstatus_SXL(mstatus));
-    match arch {
+    match architecture(mstatus[SXL]) {
       RV64 => { let mbits : bits(4) = satp[63 .. 60];
                 match satp64Mode_of_bits(RV64, mbits) {    // see riscv_types.sail
                   Some(m) => m,