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insts_base: ignore architecture in SFENCE_VMA #722

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merged 1 commit into from
Feb 10, 2025

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radimkrcmar
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Another patch from the mstatus cleanup, #683 (comment).

architecture doesn't change the behavior, so there is no reason to
complicate the code with it.

The code is still suboptimal because of rhs duplication, so this should
be rewritten if (when) Sail supports multiple matches like:
  User    or (Supervisor if mstatus[TVM] == 0b1) => ...
  Machine or (Supervisor if mstatus[TVM] == 0b0) => ...

(Separately mapping those four cases into two and matching on the two is
 also an option, but I'm not sure it would be clearer.)

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
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github-actions bot commented Feb 8, 2025

Test Results

392 tests  ±0   392 ✅ ±0   1m 21s ⏱️ -1s
  1 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 825a625. ± Comparison against base commit 8ca0ac0.

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@jordancarlin jordancarlin left a comment

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LGTM

@jordancarlin jordancarlin added the will be merged Scheduled to be merged in a few days if nobody objects label Feb 9, 2025
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@Timmmm Timmmm left a comment

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LGTM. Any idea why it was there in the first place?

@jordancarlin
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Any idea why it was there in the first place?

Looks like a remnant from this version from 7 years ago:

function clause execute SFENCE_VMA(rs1, rs2) = {
  /* TODO: handle PMP/TLB synchronization when executed in M-mode. */
  if   cur_privilege == User
  then { handle_illegal(); false }
  else match (architecture(mstatus.SXL()), mstatus.TVM()) {
    (Some(RV64), true)  => { handle_illegal(); false },
    (Some(RV64), false) => {
      let addr : option(vaddr39) = if rs1 == 0 then None() else Some(X(rs1)[38 .. 0]);
      let asid : option(asid64)  = if rs2 == 0 then None() else Some(X(rs2)[15 .. 0]);
      flushTLB(asid, addr);
      true
    },
    (_, _) => internal_error("unimplemented sfence architecture")
  }
}

Seemingly it only supported RV64 at the time.

@Timmmm Timmmm merged commit f07976f into riscv:master Feb 10, 2025
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4 participants