Add support for Zcmp extension

Makefile.old

@@ -40,6 +40,7 @@ SAIL_DEFAULT_INST += riscv_insts_zbc.sail
 SAIL_DEFAULT_INST += riscv_insts_zbs.sail
 
 SAIL_DEFAULT_INST += riscv_insts_zcb.sail
+SAIL_DEFAULT_INST += riscv_insts_zcmp.sail
 
 SAIL_DEFAULT_INST += riscv_insts_zfh.sail
 # Zfa needs to be added after fext, dext and Zfh (as it needs

c_emulator/riscv_platform.c

@@ -37,6 +37,16 @@ bool sys_enable_zcb(unit u)
   return rv_enable_zcb;
 }
 
+bool sys_enable_zcd(unit u)
+{
+  return rv_enable_zcd;
+}
+
+bool sys_enable_zcmp(unit u)
+{
+  return rv_enable_zcmp;
+}
+
 bool sys_enable_zfinx(unit u)
 {
   return rv_enable_zfinx;

c_emulator/riscv_platform.h

@@ -5,6 +5,8 @@ bool sys_enable_rvc(unit);
 bool sys_enable_fdext(unit);
 bool sys_enable_svinval(unit);
 bool sys_enable_zcb(unit);
+bool sys_enable_zcd(unit);
+bool sys_enable_zcmp(unit);
 bool sys_enable_zfinx(unit);
 bool sys_enable_writable_misa(unit);
 bool sys_enable_writable_fiom(unit);

c_emulator/riscv_platform_impl.c

@@ -11,6 +11,8 @@ uint64_t rv_vector_elen_exp = 0x6;
 
 bool rv_enable_svinval = false;
 bool rv_enable_zcb = false;
+bool rv_enable_zcd = true;
+bool rv_enable_zcmp = false;
 bool rv_enable_zfinx = false;
 bool rv_enable_rvc = true;
 bool rv_enable_writable_misa = true;

c_emulator/riscv_platform_impl.h

@@ -16,6 +16,8 @@ extern uint64_t rv_vector_elen_exp;
 
 extern bool rv_enable_svinval;
 extern bool rv_enable_zcb;
+extern bool rv_enable_zcd;
+extern bool rv_enable_zcmp;
 extern bool rv_enable_zfinx;
 extern bool rv_enable_rvc;
 extern bool rv_enable_fdext;

c_emulator/riscv_sim.c

@@ -50,6 +50,8 @@ enum {
   OPT_PMP_GRAIN,
   OPT_ENABLE_SVINVAL,
   OPT_ENABLE_ZCB,
+  OPT_ENABLE_ZCD,
+  OPT_ENABLE_ZCMP,
   OPT_ENABLE_ZICBOM,
   OPT_ENABLE_ZICBOZ,
   OPT_ENABLE_SSTC,
@@ -148,6 +150,7 @@ static struct option options[] = {
     {"enable-writable-fiom",        no_argument,       0, OPT_ENABLE_WRITABLE_FIOM},
     {"enable-svinval",              no_argument,       0, OPT_ENABLE_SVINVAL      },
     {"enable-zcb",                  no_argument,       0, OPT_ENABLE_ZCB          },
+    {"enable-zcmp",                 no_argument,       0, OPT_ENABLE_ZCMP         },
     {"enable-zicbom",               no_argument,       0, OPT_ENABLE_ZICBOM       },
     {"enable-zicboz",               no_argument,       0, OPT_ENABLE_ZICBOZ       },
     {"cache-block-size",            required_argument, 0, OPT_CACHE_BLOCK_SIZE    },
@@ -388,6 +391,16 @@ static int process_args(int argc, char **argv)
       fprintf(stderr, "enabling Zcb extension.\n");
       rv_enable_zcb = true;
       break;
+    case OPT_ENABLE_ZCD:
+      fprintf(stderr, "enabling Zcd extension.\n");
+      rv_enable_zcd = true;
+      rv_enable_zcmp = false;
+      break;
+    case OPT_ENABLE_ZCMP:
+      fprintf(stderr, "enabling Zcmp extension.\n");
+      rv_enable_zcd = false;
+      rv_enable_zcmp = true;
+      break;
     case OPT_ENABLE_ZICBOM:
       fprintf(stderr, "enabling Zicbom extension.\n");
       rv_enable_zicbom = true;

model/CMakeLists.txt

@@ -66,6 +66,7 @@ foreach (xlen IN ITEMS 32 64)
                 "riscv_insts_zbc.sail"
                 "riscv_insts_zbs.sail"
                 "riscv_insts_zcb.sail"
+                "riscv_insts_zcmp.sail"
                 "riscv_insts_zfh.sail"
                 # Zfa needs to be added after fext, dext and Zfh (as it needs
                 # definitions from those)

model/riscv_extensions.sail

@@ -71,6 +71,8 @@ enum clause extension = Ext_Zcb
 enum clause extension = Ext_Zcd
 // Code Size Reduction: compressed single precision floating point loads and stores
 enum clause extension = Ext_Zcf
+// Code Size Reduction: compressed push/pop and double move instructions
+enum clause extension = Ext_Zcmp
 
 // Bit Manipulation: Address generation
 enum clause extension = Ext_Zba

model/riscv_insts_zcd.sail

@@ -6,7 +6,7 @@
 /*  SPDX-License-Identifier: BSD-2-Clause                                                */
 /*=======================================================================================*/
 
-function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (xlen == 32 | xlen == 64)
+function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & sys_enable_zcd() & not(sys_enable_zcmp()) & (xlen == 32 | xlen == 64)
 
 union clause ast = C_FLDSP : (bits(6), regidx)