make.txt

## Make notes

To generate dependencies for Make we can use -M family of options of
gcc/clang:

  >  gcc -MM *.c
  hex2base64.o: hex2base64.c hex.h base64.h
  my-base64.o: my-base64.c base64.h
  ...

  More details here:
  https://clang.llvm.org/docs/ClangCommandLineReference.html#dependency-file-generation
  http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/


Make use of implicit rules, "Make" already knows how to compile obj
files from .c!


Automatic variables of Make are extremely useful:

    $@ for target
    $< for the first dependency
    $^ for all dependencies w/o duplicates.

  Example:

    count_words: count_words.o counter.o lexer.o
       gcc $^ -o $@


Pattern rules look like this:

  %.o: %.c
    $(COMPILE.c) $(OUTPUT_OPTION) $<

  %: %.o  # no suffix is also fine

  They are more powerful and modern than old .SUFFIXES: approach and
  ".c.o:" rules.


Prepending command with @ does not print it while Makefile is running:

  Example (does not print 'echo test' command, just prints 'test'):

    @echo test


VPATH (and `vpath`) can be used to add source directories.


`CPPFLAGS = -I include` can be used to add directories with header
files.


Use `make -n` for dry-runs, when Make only prints what it's going to
do.


Use `make -p` to print its database of implicit rules and variables.


Minimal nice Makefile for many one-file executables (like exercises in
the book), no header files:

  CFLAGS = -g -Wall -Wextra -Werror -pedantic -std=c99

  binaries = p1 p2

  all: $(binaries)

  .PHONY: clean
  clean:
     rm -r -f *.o $(binaries) *.dSYM

Resolving of `-l<lib_name>` dependencies:

https://www.gnu.org/software/make/manual/make.html#Libraries_002fSearch