diff --git a/src/Bayeux/Rtlil.hs b/src/Bayeux/Rtlil.hs
index bc620a2..97677c6 100644
--- a/src/Bayeux/Rtlil.hs
+++ b/src/Bayeux/Rtlil.hs
@@ -19,10 +19,11 @@ module Bayeux.Rtlil
     Module(..)
   , ModuleStmt(..)
   , ModuleBody(..)
-  , initial
   , ParamStmt(..)
   , Constant(..)
   , ModuleEndStmt(..)
+  , initial
+  , counter
   , -- ** Attribute statements
     AttrStmt(..)
   , -- ** Signal specifications
@@ -45,8 +46,10 @@ module Bayeux.Rtlil
   , CellType(..)
   , CellBodyStmt(..)
   , CellEndStmt(..)
-  , -- *** Binary operators
-    andC
+  , -- *** Binary cells
+    binaryCell
+  , shiftCell
+  , andC
   , orC
   , xorC
   , xnorC
@@ -193,21 +196,6 @@ instance Pretty ModuleBody where
     ModuleBodyProcess   p -> pretty p
     ModuleBodyConnStmt  c -> pretty c
 
-initial
-  :: FiniteBits output
-  => Text -- ^ output identifier
-  -> output
-  -> [ModuleBody]
-initial outputIdent output =
-  [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 1] $ WireId $ Ident outputIdent
-  , ModuleBodyConnStmt $ ConnStmt
-      (SigSpecWireId $ WireId $ Ident outputIdent)
-      (SigSpecConstant value)
-  ]
-  where
-    value = let size = fromIntegral $ finiteBitSize output
-                bs   = binaryDigits output
-            in ConstantValue $ Value size bs
 
 data ParamStmt = ParamStmt Ident (Maybe Constant)
   deriving (Eq, Read, Show)
@@ -236,6 +224,58 @@ data ModuleEndStmt = ModuleEndStmt
 instance Pretty ModuleEndStmt where
   pretty _ = "end" <> hardline
 
+initial
+  :: FiniteBits output
+  => Text -- ^ output identifier
+  -> output
+  -> [ModuleBody]
+initial outputIdent output =
+  [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth 1] $ WireId $ Ident outputIdent
+  , ModuleBodyConnStmt $ ConnStmt
+      (SigSpecWireId $ WireId $ Ident outputIdent)
+      (SigSpecConstant value)
+  ]
+  where
+    value = let size = fromIntegral $ finiteBitSize output
+                bs   = binaryDigits output
+            in ConstantValue $ Value size bs
+
+counter
+  :: Integer -- ^ width
+  -> Ident   -- ^ old
+  -> Ident   -- ^ new
+  -> [ModuleBody]
+counter w old new =
+  [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId old
+  , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId new
+  , ModuleBodyCell $ addC
+      (CellId old)
+      False
+      w
+      False
+      w
+      w
+      (SigSpecWireId $ WireId old)
+      (SigSpecConstant $ ConstantInteger 1)
+      (WireId new)
+  , ModuleBodyProcess $ Process
+      []
+      "\\procStmt"
+      (ProcessBody
+         []
+         Nothing
+         []
+         [Sync
+            (SyncStmt Posedge (SigSpecWireId "\\clk"))
+            [UpdateStmt
+               (DestSigSpec $ SigSpecWireId $ WireId old)
+               (SrcSigSpec  $ SigSpecWireId $ WireId new)
+            ]
+         ]
+      )
+      ProcEndStmt
+  ]
+
 data AttrStmt = AttrStmt Ident Constant
   deriving (Eq, Read, Show)
 
diff --git a/test/Test/Bayeux/Rtlil.hs b/test/Test/Bayeux/Rtlil.hs
index cd7522b..6a20060 100644
--- a/test/Test/Bayeux/Rtlil.hs
+++ b/test/Test/Bayeux/Rtlil.hs
@@ -26,6 +26,7 @@ tests =
       , prettyTest "sbRgbaDrv" sbRgbaDrv
       , prettyTest "fiatLux"   fiatLux
       , prettyTest "add"     $ addC "\\adder" False 32 False 32 33 (SigSpecWireId "\\a") (SigSpecWireId "\\b") "\\y"
+      , prettyTest "counter" $ counter 8 "\\old" "\\new"
       ]
   , testGroup "synth"
       [ synthTest "led"     rtlilLed
diff --git a/test/Test/Bayeux/Rtlil/pretty-counter.golden b/test/Test/Bayeux/Rtlil/pretty-counter.golden
new file mode 100644
index 0000000..c618149
--- /dev/null
+++ b/test/Test/Bayeux/Rtlil/pretty-counter.golden
@@ -0,0 +1,28 @@
+[ wire width 8 \old
+
+, wire width 8 \new
+
+, cell $add \old
+
+  parameter \A_SIGNED 0
+  parameter \A_WIDTH 8
+  parameter \B_SIGNED 0
+  parameter \B_WIDTH 8
+  parameter \Y_WIDTH 8
+  connect \A \old
+  connect \B 1
+  connect \Y \new
+
+end
+
+, process \procStmt
+
+  
+
+
+  sync posedge \clk
+
+    update \old \new
+
+end
+ ]
\ No newline at end of file