From 23908613ae4471d6a7fc16c4e2a187df677bdfcc Mon Sep 17 00:00:00 2001
From: dopamane <dwc1295@gmail.com>
Date: Thu, 6 Jun 2024 03:00:15 -0700
Subject: [PATCH] Build add cell

---
 src/Bayeux/Rtlil.hs                      | 32 +++++++++++++++++++++++-
 test/Test/Bayeux/Rtlil.hs                |  1 +
 test/Test/Bayeux/Rtlil/pretty-add.golden | 12 +++++++++
 3 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 test/Test/Bayeux/Rtlil/pretty-add.golden

diff --git a/src/Bayeux/Rtlil.hs b/src/Bayeux/Rtlil.hs
index 443bff7..4d59077 100644
--- a/src/Bayeux/Rtlil.hs
+++ b/src/Bayeux/Rtlil.hs
@@ -40,6 +40,7 @@ module Bayeux.Rtlil
   , MemoryOption(..)
   , -- ** Cells
     Cell(..)
+  , add
   , CellStmt(..)
   , CellId(..)
   , CellType(..)
@@ -168,7 +169,7 @@ instance Pretty ModuleBody where
 
 initial
   :: FiniteBits output
-  => Text         -- ^ output identifier
+  => Text -- ^ output identifier
   -> output
   -> [ModuleBody]
 initial outputIdent output =
@@ -301,6 +302,35 @@ instance Pretty Cell where
     , pretty e
     ]
 
+add
+  :: CellId
+  -> Bool    -- ^ \\A_SIGNED
+  -> Integer -- ^ \\A_WIDTH
+  -> Bool    -- ^ \\B_SIGNED
+  -> Integer -- ^ \\B_WIDTH
+  -> Integer -- ^ \\Y_WIDTH
+  -> SigSpec -- ^ A
+  -> SigSpec -- ^ B
+  -> WireId  -- ^ Y
+  -> Cell
+add n aSigned aWidth bSigned bWidth yWidth a b y = Cell
+  []
+  (CellStmt "$add" n)
+  [ CellParameter Nothing "\\A_SIGNED" $ ConstantInteger $ fromBool aSigned
+  , CellParameter Nothing "\\A_WIDTH"  $ ConstantInteger aWidth
+  , CellParameter Nothing "\\B_SIGNED" $ ConstantInteger $ fromBool bSigned
+  , CellParameter Nothing "\\B_WIDTH"  $ ConstantInteger bWidth
+  , CellParameter Nothing "\\Y_WIDTH"  $ ConstantInteger yWidth
+  , CellConnect "\\A" a
+  , CellConnect "\\B" b
+  , CellConnect "\\Y" $ SigSpecWireId y
+  ]
+  CellEndStmt
+  where
+    fromBool :: Bool -> Integer
+    fromBool True  = 1
+    fromBool False = 0
+
 data CellStmt = CellStmt CellType CellId
   deriving (Eq, Read, Show)
 
diff --git a/test/Test/Bayeux/Rtlil.hs b/test/Test/Bayeux/Rtlil.hs
index 89eca91..3b1f10c 100644
--- a/test/Test/Bayeux/Rtlil.hs
+++ b/test/Test/Bayeux/Rtlil.hs
@@ -25,6 +25,7 @@ tests =
       [ prettyTest "led"       rtlilLed
       , prettyTest "sbRgbaDrv" sbRgbaDrv
       , prettyTest "fiatLux"   fiatLux
+      , prettyTest "add"     $ add "\\adder" False 32 False 32 33 (SigSpecWireId "\\a") (SigSpecWireId "\\b") "\\y"
       ]
   , testGroup "synth"
       [ synthTest "led"     rtlilLed
diff --git a/test/Test/Bayeux/Rtlil/pretty-add.golden b/test/Test/Bayeux/Rtlil/pretty-add.golden
new file mode 100644
index 0000000..4b66494
--- /dev/null
+++ b/test/Test/Bayeux/Rtlil/pretty-add.golden
@@ -0,0 +1,12 @@
+cell $add \adder
+
+  parameter \A_SIGNED 0
+  parameter \A_WIDTH 32
+  parameter \B_SIGNED 0
+  parameter \B_WIDTH 32
+  parameter \Y_WIDTH 33
+  connect \A \a
+  connect \B \b
+  connect \Y \y
+
+end