diff --git a/lib/Bayeux/RgbCounter.hs b/lib/Bayeux/RgbCounter.hs
index a384393..2cf5f43 100644
--- a/lib/Bayeux/RgbCounter.hs
+++ b/lib/Bayeux/RgbCounter.hs
@@ -27,7 +27,7 @@ newtype Rgb a = Rgb{ unRgb :: Writer [ModuleBody] a }
 
 instance MonadRgb Rgb where
   ctr = do
-    tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "$my_counter" "\\unused"
+    tell $ [ModuleBodyWire $ Wire [] $ WireStmt [WireOptionInput 1] "\\clk"] <> counter 32 "\\$my_counter" "\\unused" "$my_counter" "$procStmt"
     return $ SigSpecWireId "\\$my_counter"
 
   at sigSpec ix = do
diff --git a/lib/Bayeux/Rtlil.hs b/lib/Bayeux/Rtlil.hs
index 3ba387f..afff917 100644
--- a/lib/Bayeux/Rtlil.hs
+++ b/lib/Bayeux/Rtlil.hs
@@ -258,41 +258,45 @@ initial outputIdent output =
             in ConstantValue $ Value size bs
 
 counter
-  :: Integer -- ^ width
-  -> Ident   -- ^ old
-  -> Ident   -- ^ new
+  :: Integer  -- ^ width
+  -> WireId   -- ^ old
+  -> WireId   -- ^ new
+  -> CellId   -- ^ add
+  -> ProcStmt -- ^ update
   -> [ModuleBody]
-counter w old new =
-  [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId $ "\\" <> old
-  , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] $ WireId new
+counter w old new addId procStmt =
+  [ ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] old -- $ WireId $ "\\" <> old
+  , ModuleBodyWire $ Wire [] $ WireStmt [WireOptionWidth w] new -- $ WireId new
   , ModuleBodyCell $ addC
-      (CellId old)
+      addId
       False
       w
       False
       w
       w
-      (SigSpecWireId $ WireId $ "\\" <> old)
+      (SigSpecWireId old)
       (SigSpecConstant $ ConstantInteger 1)
-      (WireId new)
-  , ModuleBodyProcess $ Process
-      []
-      "$procStmt"
-      (ProcessBody
-         []
-         Nothing
-         []
-         [Sync
-            (SyncStmt Posedge (SigSpecWireId "\\clk"))
-            [UpdateStmt
-               (DestSigSpec $ SigSpecWireId $ WireId $ "\\" <> old)
-               (SrcSigSpec  $ SigSpecWireId $ WireId new)
-            ]
-         ]
-      )
-      ProcEndStmt
+      new
+  , ModuleBodyProcess $ updateP procStmt
+      (DestSigSpec $ SigSpecWireId old)
+      (SrcSigSpec  $ SigSpecWireId new)
   ]
 
+updateP :: ProcStmt -> DestSigSpec -> SrcSigSpec -> Process
+updateP procStmt destSig srcSig = Process
+  []
+  procStmt
+  (ProcessBody
+    []
+    Nothing
+    []
+    [Sync
+       (SyncStmt Posedge (SigSpecWireId "\\clk"))
+       [UpdateStmt destSig srcSig]
+    ]
+  )
+  ProcEndStmt
+
 data AttrStmt = AttrStmt Ident Constant
   deriving (Eq, Read, Show)
 
@@ -555,13 +559,14 @@ modC      = binaryCell . CellStmt "$mod"
 divFloorC = binaryCell . CellStmt "$divfloor"
 modFloorC = binaryCell . CellStmt "$modfloor"
 
+-- | Y = S ? B : A
 muxC
   :: CellId
-  -> Integer -- ^ \WIDTH
-  -> SigSpec -- ^ \A
-  -> SigSpec -- ^ \B
-  -> SigSpec -- ^ \S
-  -> WireId
+  -> Integer -- ^ WIDTH
+  -> SigSpec -- ^ A
+  -> SigSpec -- ^ B
+  -> SigSpec -- ^ S
+  -> WireId  -- ^ Y
   -> Cell
 muxC cellId w a b s y = Cell
   []
diff --git a/test/Test/Bayeux/Rtlil.hs b/test/Test/Bayeux/Rtlil.hs
index a3bb9cf..c9bb33d 100644
--- a/test/Test/Bayeux/Rtlil.hs
+++ b/test/Test/Bayeux/Rtlil.hs
@@ -29,7 +29,7 @@ tests =
           (SigSpecWireId "\\pwm_b")
       , prettyTest "fiatLux"   fiatLux
       , prettyTest "add"     $ addC "\\adder" False 32 False 32 33 (SigSpecWireId "\\a") (SigSpecWireId "\\b") "\\y"
-      , prettyTest "counter" $ counter 8 "\\old" "\\new"
+      , prettyTest "counter" $ counter 8 "\\old" "\\new" "$old" "$procStmt"
       ]
   , testGroup "synth"
       [ synthTest "led"     rtlilLed
diff --git a/test/Test/Bayeux/Rtlil/golden/counter.pretty b/test/Test/Bayeux/Rtlil/golden/counter.pretty
index 34466cf..8196b51 100644
--- a/test/Test/Bayeux/Rtlil/golden/counter.pretty
+++ b/test/Test/Bayeux/Rtlil/golden/counter.pretty
@@ -1,13 +1,13 @@
-[ wire width 8 \\old
+[ wire width 8 \old
 , wire width 8 \new
 , 
-cell $add \old
+cell $add $old
   parameter \A_SIGNED 0
   parameter \A_WIDTH 8
   parameter \B_SIGNED 0
   parameter \B_WIDTH 8
   parameter \Y_WIDTH 8
-  connect \A \\old
+  connect \A \old
   connect \B 1
   connect \Y \new
 end
@@ -18,6 +18,6 @@ process $procStmt
 
 
   sync posedge \clk
-    update \\old \new
+    update \old \new
 end
  ]
\ No newline at end of file