diff --git a/data/BufEcho.pcf b/data/EchoLine.pcf
similarity index 100%
rename from data/BufEcho.pcf
rename to data/EchoLine.pcf
diff --git a/exe/Main.hs b/exe/Main.hs
index 773953f..7400659 100644
--- a/exe/Main.hs
+++ b/exe/Main.hs
@@ -36,7 +36,11 @@ parseDemo = asum
   , flag' Hello $ long "Hello" <> help "Hello demo"
   , flag' Echo $ long "Echo" <> help "Echo demo"
   , flag' LedCtrl $ long "LedCtrl" <> help "Control Led IP through UART"
-  , flag' BufEcho $ long "BufEcho" <> help "BufEcho demo"
+  , flag' SpramReverse $ mconcat
+    [ long "SpramReverse"
+    , help "SpramReverse demo: Send bytes to UART, buffer them in SPRAM, then \
+           \read the bytes LIFO."
+    ]
   ]
 
 parseProve :: Parser Prove
diff --git a/lib/Bayeux.hs b/lib/Bayeux.hs
index bea7a8b..0ddc295 100644
--- a/lib/Bayeux.hs
+++ b/lib/Bayeux.hs
@@ -43,13 +43,13 @@ app = \case
 
 getDemo :: Demo -> File
 getDemo = \case
-  FiatLux    -> fiatLux
-  RgbCounter -> rgbCounter
-  RgbCycle   -> rgbCycle
-  Hello      -> handleErr $ compile hello
-  Echo       -> handleErr $ compile echo
-  LedCtrl    -> handleErr $ compile ledCtrl
-  BufEcho    -> handleErr $ compile bufEcho
+  FiatLux      -> fiatLux
+  RgbCounter   -> rgbCounter
+  RgbCycle     -> rgbCycle
+  Hello        -> handleErr $ compile hello
+  Echo         -> handleErr $ compile echo
+  LedCtrl      -> handleErr $ compile ledCtrl
+  SpramReverse -> handleErr $ compile spramReverse
 
 rgbCounter :: File
 rgbCounter = handleErr $ compile prog
diff --git a/lib/Bayeux/Cell.hs b/lib/Bayeux/Cell.hs
index b59259d..38573af 100644
--- a/lib/Bayeux/Cell.hs
+++ b/lib/Bayeux/Cell.hs
@@ -4,6 +4,7 @@
 module Bayeux.Cell
   ( -- * Unary
     inc
+  , dec
   , logicNot
   , not
   , -- * Binary
@@ -60,6 +61,9 @@ import Prelude hiding (and, div, mod, not, or)
 inc :: Encode a => Width a => MonadSignal m => Sig a -> m (Sig a)
 inc a = binary addC a $ sig True
 
+dec :: Encode a => Width a => MonadSignal m => Sig a -> m (Sig a)
+dec a = binary subC a $ sig True
+
 logicNot :: MonadSignal m => Sig Bool -> m (Sig Bool)
 logicNot = unary logicNotC
 
diff --git a/lib/Bayeux/Cli.hs b/lib/Bayeux/Cli.hs
index 7d08749..1f6f27b 100644
--- a/lib/Bayeux/Cli.hs
+++ b/lib/Bayeux/Cli.hs
@@ -22,7 +22,7 @@ data Demo = FiatLux
           | Hello
           | Echo
           | LedCtrl
-          | BufEcho
+          | SpramReverse
   deriving (Eq, Read, Show)
 
 data Prove = Prove
diff --git a/lib/Bayeux/Ice40/Spram.hs b/lib/Bayeux/Ice40/Spram.hs
index 3c30c1c..82a46bc 100644
--- a/lib/Bayeux/Ice40/Spram.hs
+++ b/lib/Bayeux/Ice40/Spram.hs
@@ -5,9 +5,12 @@
 
 module Bayeux.Ice40.Spram
   ( spramC
-  , Addr14(..)
+  , Word14(..)
   , Word4(..)
   , MonadSpram(..)
+  , Req(..)
+  , rSig
+  , wSig
   , memory
   ) where
 
@@ -51,14 +54,14 @@ spramC name a din maskWrEn wren cs clk sb slp pwrOff dout = Cell
   ]
   CellEndStmt
 
-newtype Addr14 = Addr14{ unAddr14 :: Array (Finite 14) Bool }
+newtype Word14 = Word14{ unWord14 :: Array (Finite 14) Bool }
   deriving (Encode, Eq, Read, Show, Width)
 
 newtype Word4 = Word4{ unWord4 :: Array (Finite 4) Bool }
   deriving (Encode, Eq, Read, Show, Width)
 
 class MonadSpram m where
-  spram :: Sig Addr14     -- ^ address
+  spram :: Sig Word14     -- ^ address
         -> Sig Word16     -- ^ data in
         -> Sig Word4      -- ^ mask write enable
         -> Sig Bool       -- ^ write enable
@@ -86,8 +89,8 @@ instance MonadSpram Rtl where
       dout]
     return $ Sig dout
 
-data Req = R Addr14
-         | W Addr14 Word16 Word4
+data Req = R Word14
+         | W Word14 Word16 Word4
   deriving (Eq, Read, Show)
 
 instance Width Req where
@@ -101,7 +104,7 @@ instance Encode Req where
 sliceWrEn :: Sig Req -> Sig Bool
 sliceWrEn = slice 34 34
 
-sliceAddr :: Sig Req -> Sig Addr14
+sliceAddr :: Sig Req -> Sig Word14
 sliceAddr = slice 33 20
 
 sliceDataIn :: Sig Req -> Sig Word16
@@ -110,6 +113,12 @@ sliceDataIn = slice 19 4
 sliceMaskWrEn :: Sig Req -> Sig Word4
 sliceMaskWrEn = slice 3 0
 
+rSig :: Sig Word14 -> Sig Req
+rSig a = Sig $ (spec . sig) False <> spec a <> fromString ("20'" <> replicate 20 '0')
+
+wSig :: Sig Word14 -> Sig Word16 -> Sig Word4 -> Sig Req
+wSig a d m = Sig $ (spec . sig) True <> spec a <> spec d <> spec m
+
 memory
   :: Monad       m
   => MonadSignal m
diff --git a/lib/Bayeux/Uart.hs b/lib/Bayeux/Uart.hs
index f32bcc6..908c277 100644
--- a/lib/Bayeux/Uart.hs
+++ b/lib/Bayeux/Uart.hs
@@ -1,4 +1,5 @@
 {-# LANGUAGE DataKinds           #-}
+{-# LANGUAGE FlexibleContexts    #-}
 {-# LANGUAGE OverloadedLists     #-}
 {-# LANGUAGE OverloadedStrings   #-}
 {-# LANGUAGE ScopedTypeVariables #-}
@@ -7,29 +8,33 @@ module Bayeux.Uart
   ( MonadUart(..)
   , hello
   , echo
-  , bufEcho
+  , spramReverse
   ) where
 
 import Bayeux.Buffer
 import Bayeux.Cell
 import Bayeux.Encode
+import Bayeux.Ice40.Spram
 import Bayeux.Rtl hiding (at, binary, mux, process, shift, shr, unary)
 import Bayeux.Signal
 import Bayeux.Width
 import Control.Monad
+import Control.Monad.Writer
 import Data.Array
 import Data.Bits hiding (shift)
-import Data.Finite
+import Data.Char
+import Data.Finite hiding (sub)
 import Data.Proxy
 import Data.Word
 
 class MonadUart m where
-  transmit :: Word16 -- ^ baud
+  transmit :: Word16                -- ^ baud
            -> Sig (Maybe Word8)
-           -> m ()
-  receive :: Word16   -- ^ baud
-          -> Sig Bool -- ^ rx
-          -> m (Sig (Maybe Word8))
+           -> m (Sig Bool)          -- ^ busy=True, idle=False
+
+  receive  :: Word16                -- ^ baud
+           -> Sig Bool              -- ^ rx
+           -> m (Sig (Maybe Word8))
 
 data Fsm = Idle | Start | Recv | Stop
   deriving (Enum, Eq, Read, Show)
@@ -41,7 +46,7 @@ instance Encode Fsm where
   encode = encode . finiteProxy (Proxy :: Proxy 4) . fromIntegral . fromEnum
 
 instance MonadUart Rtl where
-  transmit baud byte = void $ process $ \txFsm -> do
+  transmit baud byte = process $ \txFsm -> do
     isStart <- txFsm === sig False
     txCtr <- process $ \txCtr -> ifm
       [ (pure isStart .|| txCtr === sig baud) `thenm` val 0
@@ -111,18 +116,113 @@ instance MonadUart Rtl where
 hello :: Monad m => MonadUart m => MonadSignal m => m (Sig Word32)
 hello = process $ \timer -> do
   is5Sec <- timer === sig 60000000
-  transmit 624 $ toMaybeSig is5Sec $ sig 0x61
+  _ <- transmit 624 $ toMaybeSig is5Sec $ sig 0x61
   flip (mux is5Sec) (sig 0) =<< inc timer
 
-echo :: Monad m => MonadUart m => MonadSignal m => m ()
+echo :: Monad m => MonadUart m => MonadSignal m => m (Sig Bool)
 echo = transmit 624 =<< receive 624 =<< input "\\rx"
 
-bufEcho :: Monad m => MonadBuffer m => MonadSignal m => MonadUart m => m ()
-bufEcho = do
-  b <- buf =<< receive 624 =<< input "\\rx"
-  transmit 624 =<< cobuf b
+data ELFsm = Buffering | Cobuffering
+  deriving (Eq, Read, Show)
+
+instance Width ELFsm where
+  width _ = 1
+
+instance Encode ELFsm where
+  encode Buffering   = [B0]
+  encode Cobuffering = [B1]
+
+data EchoLine = EchoLine
+  { rwAddr :: Word14
+  , elFsm  :: ELFsm
+  }
+  deriving (Eq, Read, Show)
+
+instance Width EchoLine where
+  width _ = 15
+
+instance Encode EchoLine where
+  encode el = encode (rwAddr el) <> encode (elFsm el)
+
+sliceRWAddr :: Sig EchoLine -> Sig Word14
+sliceRWAddr = slice 14 1
+
+sliceELFsm :: Sig EchoLine -> Sig ELFsm
+sliceELFsm = slice 0 0
+
+spramReverse
+  :: Monad       m
+  => MonadBuffer m
+  => MonadRtl    m
+  => MonadSignal m
+  => MonadSpram  m
+  => MonadUart   m
+  => MonadWriter [ModuleBody] m
+  => m (Sig EchoLine)
+spramReverse = do
+  wM <- receive 624 =<< input "\\rx"
+  isNewline <- (sig . fromIntegral . ord) '\n' === sliceValue wM
+  notNewline <- logicNot isNewline
+  process $ \s -> do
+    let rwAddrSig = sliceRWAddr s
+        fsm = sliceELFsm s
+    rAddr <- rwAddrSig `sub` Sig "14'00000000000001"
+    isEmpty <- rAddr === (Sig "14'00000000000000")
+    txBusy <- (\txBusy -> do
+      txIdle <- logicNot txBusy
+      isWrite <- sliceValid wM `logicAnd` notNewline
+      pats fsm
+        [ Buffering ~~> toMaybeSig
+          isWrite
+          (wSig
+            rwAddrSig
+            (Sig $ "8'00000000" <> (spec . sliceValue) wM)
+            (Sig "4'0011")
+          )
+        , Cobuffering ~~> toMaybeSig txIdle (rSig rAddr)
+        ]) >-< (transmit 624 . repack <=< memory)
+    txIdle' <- process $ const $ logicNot txBusy
+    isWrite <- sliceValid wM `logicAnd` notNewline
+    isRead <- txBusy `logicAnd` txIdle' -- from idle to busy
+    rwAddrSig' <- patm fsm
+      [ Buffering ~> ifm
+        [ pure isWrite `thenm` (inc rwAddrSig)
+        , elsem $ pure rwAddrSig
+        ]
+      , Cobuffering ~> ifm
+        [ pure isRead `thenm` (dec rwAddrSig)
+        , elsem $ pure rwAddrSig
+        ]
+      ]
+    fsm' <- patm fsm
+      [ Buffering ~> patm wM
+        [ (Just . fromIntegral . ord) '\n' ~> val Cobuffering
+        , wildm $ pure fsm
+        ]
+      , Cobuffering ~> ifm
+        [ (isRead `logicAnd` isEmpty) `thenm` val Buffering
+        , elsem $ pure fsm
+        ]
+      ]
+    return $ Sig $ spec rwAddrSig' <> spec fsm'
   where
-    buf :: MonadBuffer m => Sig (Maybe Word8) -> m (Sig (Maybe (Array (Finite 1) Word8)))
-    buf = buffer
-    cobuf :: MonadBuffer m => Sig (Maybe (Array (Finite 1) Word8)) -> m (Sig (Maybe Word8))
-    cobuf = cobuffer
+    repack :: Sig (Maybe Word16) -> Sig (Maybe Word8)
+    repack s = Sig $ (spec . sliceValid) s <> (spec . slice 7 0 . sliceValue) s
+
+-- | Interconnect. Create a `Sig a`. Apply it to the first argument. Apply the result
+-- to the second argument. Connect the result to the `Sig a`.
+(>-<)
+  :: forall m a b
+   . Monad       m
+  => MonadRtl    m
+  => MonadSignal m
+  => MonadWriter [ModuleBody] m
+  => Width a
+  => (Sig a -> m (Sig b))
+  -> (Sig b -> m (Sig a))
+  -> m (Sig a)
+f >-< g = do
+  a  <- freshWire (width (undefined :: a))
+  a' <- g =<< f (Sig a)
+  tell [ModuleBodyConnStmt $ ConnStmt a (spec a')]
+  return $ Sig a
diff --git a/test/Test/Bayeux/Uart.hs b/test/Test/Bayeux/Uart.hs
index 2d90fb7..f9edf42 100644
--- a/test/Test/Bayeux/Uart.hs
+++ b/test/Test/Bayeux/Uart.hs
@@ -23,12 +23,12 @@ tests =
   [ testGroup "pretty"
       [ prettyTest "hello" $ handleErr $ compile hello
       , prettyTest "echo"  $ handleErr $ compile echo
-      , prettyTest "bufEcho" $ handleErr $ compile bufEcho
+      , prettyTest "spramReverse" $ handleErr $ compile spramReverse
       ]
   , testGroup "synth"
       [ synthTest "hello" $ handleErr $ compile hello
       , synthTest "echo"  $ handleErr $ compile echo
-      , synthTest "bufEcho" $ handleErr $ compile bufEcho
+      , synthTest "spramReverse" $ handleErr $ compile spramReverse
       ]
   ]
 
diff --git a/test/Test/Bayeux/Uart/golden/bufEcho.pretty b/test/Test/Bayeux/Uart/golden/spramReverse.pretty
similarity index 66%
rename from test/Test/Bayeux/Uart/golden/bufEcho.pretty
rename to test/Test/Bayeux/Uart/golden/spramReverse.pretty
index 71f695a..45206b1 100644
--- a/test/Test/Bayeux/Uart/golden/bufEcho.pretty
+++ b/test/Test/Bayeux/Uart/golden/spramReverse.pretty
@@ -476,678 +476,719 @@ module \top
       update \wire7 { \wire85 \wire77 }
   end
 
-  wire width 1 \wire87
-  wire width 1 \wire89
+  wire width 8 \wire87
 
-  cell $eq $cell90
+  cell $eq $cell88
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 8
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire87
-    connect \B 1'0
-    connect \Y \wire89
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 8
+    connect \A 8'00001010
+    connect \B { \wire52 \wire42 } [7:0]
+    connect \Y \wire87
   end
 
-  wire width 1 \wire91
-  connect \wire91 \wire89 [0]
-  wire width 1 \wire92
+  wire width 1 \wire89
+  connect \wire89 \wire87 [0]
+  wire width 1 \wire90
 
-  cell $add $cell93
+  cell $logic_not $cell91
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire87
-    connect \B 1'1
-    connect \Y \wire92
+    connect \A \wire89
+    connect \Y \wire90
   end
 
-  wire width 1 \wire94
+  wire width 15 \wire92
+  wire width 14 \wire94
 
-  cell $mux $cell95
-    parameter \WIDTH 1
-    connect \A \wire92
-    connect \B 1'0
-    connect \S \wire91
+  cell $sub $cell95
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 14
+    parameter \Y_WIDTH 14
+    connect \A \wire92 [14:1]
+    connect \B 14'00000000000001
     connect \Y \wire94
   end
 
-  wire width 1 \wire96
+  wire width 14 \wire96
 
-  cell $mux $cell97
-    parameter \WIDTH 1
-    connect \A \wire87
-    connect \B \wire94
-    connect \S { \wire52 \wire42 } [8:8]
+  cell $eq $cell97
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 14
+    parameter \Y_WIDTH 14
+    connect \A \wire94
+    connect \B 14'00000000000000
     connect \Y \wire96
   end
 
-
-  process $proc88
-    
-
-
-    sync posedge \clk
-      update \wire87 \wire96
-  end
-
   wire width 1 \wire98
+  connect \wire98 \wire96 [0]
+  wire width 1 \wire99
+  wire width 1 \wire100
 
-  cell $eq $cell99
+  cell $logic_not $cell101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire87
-    connect \B 1'0
-    connect \Y \wire98
+    connect \A \wire99
+    connect \Y \wire100
   end
 
-  wire width 1 \wire100
-  connect \wire100 \wire98 [0]
-  wire width 8 \wire101
-  wire width 8 \wire103
+  wire width 1 \wire102
 
-  cell $shr $cell104
+  cell $logic_and $cell103
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A \wire101
-    connect \B 8'00001000
-    connect \Y \wire103
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A { \wire52 \wire42 } [8:8]
+    connect \B \wire90
+    connect \Y \wire102
   end
 
-  wire width 8 \wire105
+  wire width 1 \wire104
 
-  cell $and $cell106
+  cell $eq $cell105
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A \wire103
-    connect \B 8'00000000
-    connect \Y \wire105
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire92 [0:0]
+    connect \B 1'0
+    connect \Y \wire104
   end
 
-  wire width 8 \wire107
+  wire width 1 \wire106
+  connect \wire106 \wire104 [0]
+  wire width 1 \wire107
 
-  cell $or $cell108
+  cell $eq $cell108
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A { { \wire52 \wire42 } [7:0] 0' }
-    connect \B \wire105
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire92 [0:0]
+    connect \B 1'1
     connect \Y \wire107
   end
 
-  wire width 8 \wire109
+  wire width 1 \wire109
+  connect \wire109 \wire107 [0]
+  wire width 36 \wire110
 
-  cell $mux $cell110
-    parameter \WIDTH 8
-    connect \A \wire101
-    connect \B \wire107
-    connect \S { \wire52 \wire42 } [8:8]
-    connect \Y \wire109
+  cell $mux $cell111
+    parameter \WIDTH 36
+    connect \A { \wire100 1'0 \wire94 20'00000000000000000000 }
+    connect \B { \wire102 1'1 \wire92 [14:1] 8'00000000 { \wire52 \wire42 } [7:0] 4'0011 }
+    connect \S \wire106
+    connect \Y \wire110
   end
 
+  wire width 16 \wire113
+  attribute \module_not_derived 1
+  cell \SB_SPRAM256KA \SB_SPRAM256KA_INST112
+    connect \ADDRESS \wire110 [34:0] [33:20]
+    connect \DATAIN \wire110 [34:0] [19:4]
+    connect \MASKWREN \wire110 [34:0] [3:0]
+    connect \WREN \wire110 [34:0] [34:34]
+    connect \CHIPSELECT \wire110 [35:35]
+    connect \CLOCK \clk
+    connect \STANDBY 1'0
+    connect \SLEEP 1'0
+    connect \POWEROFF 1'1
+    connect \DATAOUT \wire113
+  end
 
-  process $proc102
-    
-
+  wire width 1 \wire114
+  wire width 1 \wire116
 
-    sync posedge \clk
-      update \wire101 \wire109
+  cell $logic_not $cell117
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire110 [34:0] [34:34]
+    connect \Y \wire116
   end
 
-  wire width 1 \wire111
-  wire width 1 \wire113
+  wire width 1 \wire118
 
-  cell $logic_and $cell114
+  cell $logic_and $cell119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire100
-    connect \B { \wire52 \wire42 } [8:8]
-    connect \Y \wire113
+    connect \A \wire110 [35:35]
+    connect \B \wire116
+    connect \Y \wire118
   end
 
 
-  process $proc112
+  process $proc115
     
 
 
     sync posedge \clk
-      update \wire111 \wire113
-  end
-
-  wire width 11 \wire115
-  wire width 1 \wire117
-
-  cell $eq $cell118
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire115 [10:10]
-    connect \B 1'0
-    connect \Y \wire117
+      update \wire114 \wire118
   end
 
-  wire width 1 \wire119
-  connect \wire119 \wire117 [0]
   wire width 1 \wire120
+  wire width 1 \wire122
 
-  cell $eq $cell121
+  cell $eq $cell123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire115 [10:10]
-    connect \B 1'1
-    connect \Y \wire120
+    connect \A \wire120
+    connect \B 1'0
+    connect \Y \wire122
   end
 
-  wire width 1 \wire122
-  connect \wire122 \wire120 [0]
-  wire width 1 \wire123
+  wire width 1 \wire124
+  connect \wire124 \wire122 [0]
+  wire width 16 \wire125
+  wire width 16 \wire127
 
-  cell $eq $cell124
+  cell $eq $cell128
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 16
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire115 [9:9]
-    connect \B 1'0
-    connect \Y \wire123
+    parameter \B_WIDTH 16
+    parameter \Y_WIDTH 16
+    connect \A \wire125
+    connect \B 16'0000001001110000
+    connect \Y \wire127
   end
 
-  wire width 1 \wire125
-  connect \wire125 \wire123 [0]
-  wire width 1 \wire126
+  wire width 1 \wire129
+  connect \wire129 \wire127 [0]
+  wire width 1 \wire130
 
-  cell $logic_and $cell127
+  cell $logic_or $cell131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire122
-    connect \B \wire125
-    connect \Y \wire126
+    connect \A \wire124
+    connect \B \wire129
+    connect \Y \wire130
   end
 
-  wire width 1 \wire128
+  wire width 16 \wire132
 
-  cell $logic_and $cell129
+  cell $add $cell133
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire119
-    connect \B { \wire111 \wire101 } [8:8]
-    connect \Y \wire128
+    parameter \Y_WIDTH 16
+    connect \A \wire125
+    connect \B 1'1
+    connect \Y \wire132
   end
 
-  wire width 1 \wire130
+  wire width 16 \wire134
 
-  cell $mux $cell131
-    parameter \WIDTH 1
-    connect \A \wire115 [10:10]
-    connect \B 1'1
-    connect \S \wire128
-    connect \Y \wire130
+  cell $mux $cell135
+    parameter \WIDTH 16
+    connect \A \wire132
+    connect \B 16'0000000000000000
+    connect \S \wire130
+    connect \Y \wire134
   end
 
-  wire width 1 \wire132
 
-  cell $mux $cell133
-    parameter \WIDTH 1
-    connect \A \wire130
-    connect \B 1'0
-    connect \S \wire126
-    connect \Y \wire132
-  end
+  process $proc126
+    
 
-  wire width 1 \wire134
 
-  cell $eq $cell135
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire115 [9:9]
-    connect \B 1'0
-    connect \Y \wire134
+    sync posedge \clk
+      update \wire125 \wire134
   end
 
-  wire width 1 \wire136
-  connect \wire136 \wire134 [0]
-  wire width 1 \wire137
+  wire width 16 \wire136
 
-  cell $logic_or $cell138
+  cell $eq $cell137
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 16
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire128
-    connect \B \wire136
-    connect \Y \wire137
+    parameter \B_WIDTH 16
+    parameter \Y_WIDTH 16
+    connect \A \wire125
+    connect \B 16'0000001001110000
+    connect \Y \wire136
   end
 
+  wire width 1 \wire138
+  connect \wire138 \wire136 [0]
   wire width 1 \wire139
 
-  cell $add $cell140
+  cell $logic_not $cell140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire115 [9:9]
-    connect \B 1'1
+    connect \A \wire138
     connect \Y \wire139
   end
 
-  wire width 1 \wire141
-
-  cell $mux $cell142
-    parameter \WIDTH 1
-    connect \A \wire139
-    connect \B 1'0
-    connect \S \wire137
-    connect \Y \wire141
-  end
-
+  wire width 8 \wire141
   wire width 8 \wire143
 
-  cell $shr $cell144
+  cell $eq $cell144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 8
-    connect \A \wire115 [8:0] [7:0]
-    connect \B 8'00001000
+    connect \A \wire141
+    connect \B 8'00001001
     connect \Y \wire143
   end
 
   wire width 1 \wire145
+  connect \wire145 \wire143 [0]
+  wire width 8 \wire146
 
-  cell $eq $cell146
+  cell $add $cell147
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire115 [10:10]
-    connect \B 1'0
-    connect \Y \wire145
+    parameter \Y_WIDTH 8
+    connect \A \wire141
+    connect \B 1'1
+    connect \Y \wire146
   end
 
-  wire width 1 \wire147
-  connect \wire147 \wire145 [0]
-  wire width 9 \wire148
+  wire width 8 \wire148
 
   cell $mux $cell149
-    parameter \WIDTH 9
-    connect \A { 1'1 \wire143 }
-    connect \B { \wire111 \wire101 }
-    connect \S \wire147
+    parameter \WIDTH 8
+    connect \A \wire146
+    connect \B 8'00000000
+    connect \S \wire145
     connect \Y \wire148
   end
 
-  wire width 9 \wire150
+  wire width 8 \wire150
 
   cell $mux $cell151
-    parameter \WIDTH 9
+    parameter \WIDTH 8
     connect \A \wire148
-    connect \B 9'000000000
-    connect \S \wire126
+    connect \B \wire141
+    connect \S \wire139
     connect \Y \wire150
   end
 
 
-  process $proc116
+  process $proc142
     
 
 
     sync posedge \clk
-      update \wire115 { \wire132 \wire141 \wire150 }
+      update \wire141 \wire150
   end
 
-  wire width 1 \wire152
-  wire width 1 \wire154
+  wire width 8 \wire152
 
-  cell $eq $cell155
+  cell $eq $cell153
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 8
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire152
-    connect \B 1'0
-    connect \Y \wire154
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 8
+    connect \A \wire141
+    connect \B 8'00000000
+    connect \Y \wire152
   end
 
-  wire width 1 \wire156
-  connect \wire156 \wire154 [0]
-  wire width 16 \wire157
-  wire width 16 \wire159
+  wire width 1 \wire154
+  connect \wire154 \wire152 [0]
+  wire width 8 \wire155
 
-  cell $eq $cell160
+  cell $eq $cell156
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
+    parameter \A_WIDTH 8
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 16
-    parameter \Y_WIDTH 16
-    connect \A \wire157
-    connect \B 16'0000001001110000
-    connect \Y \wire159
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 8
+    connect \A \wire141
+    connect \B 8'00001001
+    connect \Y \wire155
   end
 
-  wire width 1 \wire161
-  connect \wire161 \wire159 [0]
-  wire width 1 \wire162
+  wire width 1 \wire157
+  connect \wire157 \wire155 [0]
+  wire width 8 \wire158
+  wire width 8 \wire160
 
-  cell $logic_or $cell163
+  cell $shr $cell161
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire156
-    connect \B \wire161
+    parameter \Y_WIDTH 8
+    connect \A \wire158
+    connect \B 1'1
+    connect \Y \wire160
+  end
+
+  wire width 8 \wire162
+
+  cell $mux $cell163
+    parameter \WIDTH 8
+    connect \A \wire160
+    connect \B \wire158
+    connect \S \wire139
     connect \Y \wire162
   end
 
-  wire width 16 \wire164
+  wire width 8 \wire164
 
-  cell $add $cell165
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 16
-    connect \A \wire157
-    connect \B 1'1
+  cell $mux $cell165
+    parameter \WIDTH 8
+    connect \A \wire162
+    connect \B \wire158
+    connect \S \wire154
     connect \Y \wire164
   end
 
-  wire width 16 \wire166
+  wire width 8 \wire166
 
   cell $mux $cell167
-    parameter \WIDTH 16
+    parameter \WIDTH 8
     connect \A \wire164
-    connect \B 16'0000000000000000
-    connect \S \wire162
+    connect \B { { \wire114 \wire113 } [16:16] { \wire114 \wire113 } [15:0] [7:0] } [7:0]
+    connect \S \wire124
     connect \Y \wire166
   end
 
 
-  process $proc158
+  process $proc159
     
 
 
     sync posedge \clk
-      update \wire157 \wire166
+      update \wire158 \wire166
   end
 
-  wire width 16 \wire168
+  wire width 1 \wire168
+  connect \wire168 \wire158 [0]
+  wire width 1 \wire169
 
-  cell $eq $cell169
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 16
-    parameter \Y_WIDTH 16
-    connect \A \wire157
-    connect \B 16'0000001001110000
-    connect \Y \wire168
+  cell $mux $cell170
+    parameter \WIDTH 1
+    connect \A \wire168
+    connect \B 1'1
+    connect \S \wire157
+    connect \Y \wire169
   end
 
-  wire width 1 \wire170
-  connect \wire170 \wire168 [0]
   wire width 1 \wire171
 
-  cell $logic_not $cell172
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wire170
+  cell $mux $cell172
+    parameter \WIDTH 1
+    connect \A \wire169
+    connect \B 1'0
+    connect \S \wire154
     connect \Y \wire171
   end
 
-  wire width 8 \wire173
-  wire width 8 \wire175
+  wire width 1 \wire173
 
-  cell $eq $cell176
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A \wire173
-    connect \B 8'00001001
-    connect \Y \wire175
+  cell $mux $cell174
+    parameter \WIDTH 1
+    connect \A \wire171
+    connect \B 1'1
+    connect \S \wire124
+    connect \Y \wire173
   end
 
-  wire width 1 \wire177
-  connect \wire177 \wire175 [0]
-  wire width 8 \wire178
+  wire output 175 \tx
+  connect \tx \wire173
+  wire width 1 \wire176
 
-  cell $add $cell179
+  cell $logic_and $cell177
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 8
-    connect \A \wire173
-    connect \B 1'1
+    parameter \Y_WIDTH 1
+    connect \A \wire138
+    connect \B \wire157
+    connect \Y \wire176
+  end
+
+  wire width 1 \wire178
+
+  cell $logic_not $cell179
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire176
     connect \Y \wire178
   end
 
-  wire width 8 \wire180
+  wire width 1 \wire180
 
   cell $mux $cell181
-    parameter \WIDTH 8
+    parameter \WIDTH 1
     connect \A \wire178
-    connect \B 8'00000000
-    connect \S \wire177
+    connect \B { { \wire114 \wire113 } [16:16] { \wire114 \wire113 } [15:0] [7:0] } [8:8]
+    connect \S \wire124
     connect \Y \wire180
   end
 
-  wire width 8 \wire182
 
-  cell $mux $cell183
-    parameter \WIDTH 8
-    connect \A \wire180
-    connect \B \wire173
-    connect \S \wire171
-    connect \Y \wire182
-  end
-
-
-  process $proc174
+  process $proc121
     
 
 
     sync posedge \clk
-      update \wire173 \wire182
+      update \wire120 \wire180
   end
 
-  wire width 8 \wire184
+  connect \wire99 \wire120
+  wire width 1 \wire182
+  wire width 1 \wire184
 
-  cell $eq $cell185
+  cell $logic_not $cell185
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A \wire173
-    connect \B 8'00000000
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire99
     connect \Y \wire184
   end
 
+
+  process $proc183
+    
+
+
+    sync posedge \clk
+      update \wire182 \wire184
+  end
+
   wire width 1 \wire186
-  connect \wire186 \wire184 [0]
-  wire width 8 \wire187
 
-  cell $eq $cell188
+  cell $logic_and $cell187
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 8
-    connect \A \wire173
-    connect \B 8'00001001
-    connect \Y \wire187
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A { \wire52 \wire42 } [8:8]
+    connect \B \wire90
+    connect \Y \wire186
   end
 
-  wire width 1 \wire189
-  connect \wire189 \wire187 [0]
-  wire width 8 \wire190
-  wire width 8 \wire192
+  wire width 1 \wire188
 
-  cell $shr $cell193
+  cell $logic_and $cell189
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 8
-    connect \A \wire190
-    connect \B 1'1
-    connect \Y \wire192
+    parameter \Y_WIDTH 1
+    connect \A \wire99
+    connect \B \wire182
+    connect \Y \wire188
   end
 
-  wire width 8 \wire194
+  wire width 14 \wire190
 
-  cell $mux $cell195
-    parameter \WIDTH 8
-    connect \A \wire192
-    connect \B \wire190
-    connect \S \wire171
-    connect \Y \wire194
+  cell $add $cell191
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 14
+    connect \A \wire92 [14:1]
+    connect \B 1'1
+    connect \Y \wire190
   end
 
-  wire width 8 \wire196
+  wire width 14 \wire192
 
-  cell $mux $cell197
-    parameter \WIDTH 8
-    connect \A \wire194
+  cell $mux $cell193
+    parameter \WIDTH 14
+    connect \A \wire92 [14:1]
     connect \B \wire190
     connect \S \wire186
-    connect \Y \wire196
+    connect \Y \wire192
   end
 
-  wire width 8 \wire198
+  wire width 1 \wire194
 
-  cell $mux $cell199
-    parameter \WIDTH 8
-    connect \A \wire196
-    connect \B { \wire122 \wire115 [8:0] [7:0] } [7:0]
-    connect \S \wire156
-    connect \Y \wire198
+  cell $eq $cell195
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire92 [0:0]
+    connect \B 1'0
+    connect \Y \wire194
   end
 
+  wire width 1 \wire196
+  connect \wire196 \wire194 [0]
+  wire width 14 \wire197
 
-  process $proc191
-    
+  cell $sub $cell198
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 14
+    connect \A \wire92 [14:1]
+    connect \B 1'1
+    connect \Y \wire197
+  end
 
+  wire width 14 \wire199
 
-    sync posedge \clk
-      update \wire190 \wire198
+  cell $mux $cell200
+    parameter \WIDTH 14
+    connect \A \wire92 [14:1]
+    connect \B \wire197
+    connect \S \wire188
+    connect \Y \wire199
   end
 
-  wire width 1 \wire200
-  connect \wire200 \wire190 [0]
   wire width 1 \wire201
 
-  cell $mux $cell202
-    parameter \WIDTH 1
-    connect \A \wire200
+  cell $eq $cell202
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire92 [0:0]
     connect \B 1'1
-    connect \S \wire189
     connect \Y \wire201
   end
 
   wire width 1 \wire203
+  connect \wire203 \wire201 [0]
+  wire width 14 \wire204
 
-  cell $mux $cell204
-    parameter \WIDTH 1
-    connect \A \wire201
-    connect \B 1'0
-    connect \S \wire186
-    connect \Y \wire203
+  cell $mux $cell205
+    parameter \WIDTH 14
+    connect \A \wire199
+    connect \B \wire192
+    connect \S \wire196
+    connect \Y \wire204
   end
 
-  wire width 1 \wire205
+  wire width 9 \wire206
+
+  cell $eq $cell207
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 9
+    parameter \Y_WIDTH 9
+    connect \A { \wire52 \wire42 }
+    connect \B 9'100001010
+    connect \Y \wire206
+  end
+
+  wire width 1 \wire208
+  connect \wire208 \wire206 [0]
+  wire width 1 \wire209
 
-  cell $mux $cell206
+  cell $mux $cell210
     parameter \WIDTH 1
-    connect \A \wire203
+    connect \A \wire92 [0:0]
     connect \B 1'1
-    connect \S \wire156
-    connect \Y \wire205
+    connect \S \wire208
+    connect \Y \wire209
   end
 
-  wire output 207 \tx
-  connect \tx \wire205
-  wire width 1 \wire208
+  wire width 1 \wire211
+
+  cell $eq $cell212
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wire92 [0:0]
+    connect \B 1'0
+    connect \Y \wire211
+  end
 
-  cell $logic_and $cell209
+  wire width 1 \wire213
+  connect \wire213 \wire211 [0]
+  wire width 1 \wire214
+
+  cell $logic_and $cell215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire170
-    connect \B \wire189
-    connect \Y \wire208
+    connect \A \wire188
+    connect \B \wire98
+    connect \Y \wire214
   end
 
-  wire width 1 \wire210
+  wire width 1 \wire216
+
+  cell $mux $cell217
+    parameter \WIDTH 1
+    connect \A \wire92 [0:0]
+    connect \B 1'0
+    connect \S \wire214
+    connect \Y \wire216
+  end
 
-  cell $logic_not $cell211
+  wire width 1 \wire218
+
+  cell $eq $cell219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wire208
-    connect \Y \wire210
+    connect \A \wire92 [0:0]
+    connect \B 1'1
+    connect \Y \wire218
   end
 
-  wire width 1 \wire212
+  wire width 1 \wire220
+  connect \wire220 \wire218 [0]
+  wire width 1 \wire221
 
-  cell $mux $cell213
+  cell $mux $cell222
     parameter \WIDTH 1
-    connect \A \wire210
-    connect \B { \wire122 \wire115 [8:0] [7:0] } [8:8]
-    connect \S \wire156
-    connect \Y \wire212
+    connect \A \wire216
+    connect \B \wire209
+    connect \S \wire213
+    connect \Y \wire221
   end
 
 
-  process $proc153
+  process $proc93
     
 
 
     sync posedge \clk
-      update \wire152 \wire212
+      update \wire92 { \wire204 \wire221 }
   end
 
 end