diff --git a/api/ruxos_posix_api/src/imp/pipe.rs b/api/ruxos_posix_api/src/imp/pipe.rs
index bb0ab0184..afc56c613 100644
--- a/api/ruxos_posix_api/src/imp/pipe.rs
+++ b/api/ruxos_posix_api/src/imp/pipe.rs
@@ -117,7 +117,6 @@ impl Pipe {
 
     pub fn write_end_close(&self) -> bool {
         let write_end_count = Arc::weak_count(&self.buffer);
-        // error!("Pipe::write_end_close <= buffer: {:#?} {:#?}", write_end_count, Arc::as_ptr(&self.buffer));
         write_end_count == 0
     }
 }
diff --git a/modules/ruxhal/src/arch/x86_64/mod.rs b/modules/ruxhal/src/arch/x86_64/mod.rs
index 973ff5cf6..a934c5b18 100644
--- a/modules/ruxhal/src/arch/x86_64/mod.rs
+++ b/modules/ruxhal/src/arch/x86_64/mod.rs
@@ -174,7 +174,6 @@ pub fn flush_tlb(vaddr: Option<VirtAddr>) {
 #[inline]
 #[cfg(all(feature = "irq", feature = "paging", feature = "smp"))]
 pub(crate) fn flush_tlb_ipi_handler() {
-    // error!("flush TLB entry in IPI handler");
     let guard = kernel_guard::NoPreempt::new();
     unsafe {
         let mut flushing_addresses = FLUSHING_ADDRESSES[this_cpu_id()].lock();