forked from chipsalliance/VeeR-ISS
-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathPerfApi.cpp
1304 lines (1066 loc) · 31.7 KB
/
PerfApi.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Copyright 2024 Tenstorrent Corporation.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <cinttypes>
#include "PerfApi.hpp"
using namespace TT_PERF;
using CSRN = WdRiscv::CsrNumber;
PerfApi::PerfApi(System64& system)
: system_(system)
{
unsigned n = system.hartCount();
traceFiles_.resize(n);
hartPacketMaps_.resize(n);
hartStoreMaps_.resize(n);
hartLastRetired_.resize(n);
hartRegProducers_.resize(n);
for (auto& producers : hartRegProducers_)
producers.resize(totalRegCount_);
}
std::shared_ptr<Hart64>
PerfApi::checkHart(const char* caller, unsigned hartIx)
{
auto hart = getHart(hartIx);
if (not hart)
{
std::cerr << caller << ": Bad hart index: " << hartIx << '\n';
assert(0);
}
return hart;
}
std::shared_ptr<InstrPac>
PerfApi::checkTag(const char* caller, unsigned hartIx, uint64_t tag)
{
auto& packetMap = hartPacketMaps_.at(hartIx);
auto iter = packetMap.find(tag);
if (iter != packetMap.end())
return iter->second;
std::cerr << caller << ": Unknown tag (never fetched): " << tag << '\n';
assert(0);
return nullptr;
}
bool
PerfApi::checkTime(const char* caller, uint64_t time)
{
if (time < time_)
{
std::cerr << caller << ": Bad time: " << time << '\n';
assert(0);
return false;
}
time_ = time;
return true;
}
bool
PerfApi::fetch(unsigned hartIx, uint64_t time, uint64_t tag, uint64_t vpc,
bool& trap, ExceptionCause& cause, uint64_t& trapPc)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_fetch %" PRIu64 " 0x%" PRIx64 "\n",
hartIx, time, tag, vpc);
auto hart = checkHart("Fetch", hartIx);
if (not hart)
return false;
if (not checkTime("Fetch", time))
return false;
if (tag == 0)
{
std::cerr << "Error in PerfApi::fetch: Hart-ix=" << hartIx << "tag=" << tag
<< " zero tag is reserved.\n";
assert(0);
return false;
}
auto& packetMap = hartPacketMaps_.at(hartIx);
if (not packetMap.empty() and packetMap.rbegin()->first >= tag)
{
std::cerr << "Error in PerfApi::fetch: Hart-ix=" << hartIx << "tag=" << tag
<< " tag is not in increasing order.\n";
assert(0);
return false;
}
auto packet = getInstructionPacket(hartIx, tag);
if (packet)
{
std::cerr << "Error in PerfApi::fetch: Hart-ix=" << hartIx << "tag=" << tag
<< " tag is already fetched.\n";
return false; // Tag already fetched.
}
auto prev = this->prevFetch_;
if (prev and not prev->predicted() and not prev->trapped() and not prev->executed())
{
bool sequential = prev->instrVa() + prev->decodedInst().instSize() == vpc;
if (not prev->decodedInst().isBranch())
{
if (not sequential)
prev->predictBranch(true, vpc);
}
else
{
if (sequential)
prev->predictBranch(false, vpc);
}
}
uint64_t ppc = 0, ppc2 = 0; // Physical pc.
uint32_t opcode = 0;
uint64_t gpc = 0; // Guest physical pc.
cause = hart->fetchInstNoTrap(vpc, ppc, ppc2, gpc, opcode);
packet = std::make_shared<InstrPac>(tag, vpc, ppc, ppc2);
assert(packet);
packet->fetched_ = true;
packet->opcode_= opcode;
insertPacket(hartIx, tag, packet);
if (not decode(hartIx, time, tag))
assert(0);
prevFetch_ = packet;
packet->trap_ = trap = cause != ExceptionCause::NONE;
if (prev and not prev->trapped() and prev->executed() and prev->nextIva_ != vpc)
{
packet->shouldFlush_ = true;
packet->flushVa_ = prev->nextIva_;
}
if (trap)
{
prevFetch_ = nullptr;
trapPc = 0;
}
return true;
}
bool
PerfApi::decode(unsigned hartIx, uint64_t time, uint64_t tag)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_decode %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Decode", time))
return false;
auto hart = checkHart("Decode", hartIx);
if (not hart)
return false;
auto packet = checkTag("Decode", hartIx, tag);
if (not packet)
return false;
if (packet->decoded())
return true;
hart->decode(packet->instrVa(), packet->instrPa(), packet->opcode_, packet->di_);
packet->decoded_ = true;
// Collect producers of operands of this instruction.
auto& di = packet->decodedInst();
auto& producers = hartRegProducers_.at(hartIx);
for (unsigned i = 0; i < di.operandCount(); ++i)
{
using OM = WdRiscv::OperandMode;
auto mode = di.ithOperandMode(i);
if (mode != OM::None)
{
unsigned regNum = di.ithOperand(i);
unsigned gri = globalRegIx(di.ithOperandType(i), regNum);
packet->opProducers_.at(i) = producers.at(gri);
}
}
// Mark this insruction as the producer of each of its destination registers.
for (unsigned i = 0; i < di.operandCount(); ++i)
{
using OM = WdRiscv::OperandMode;
auto mode = di.effectiveIthOperandMode(i);
if (mode == OM::Write or mode == OM::ReadWrite)
{
unsigned regNum = di.ithOperand(i);
unsigned gri = globalRegIx(di.ithOperandType(i), regNum);
if (regNum == 0 and di.ithOperandType(i) == WdRiscv::OperandType::IntReg)
continue; // Reg X0 has no producer
producers.at(gri) = packet;
}
}
return true;
}
bool
PerfApi::execute(unsigned hartIx, uint64_t time, uint64_t tag)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_execute %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Execute", time))
return false;
auto hartPtr = checkHart("Execute", hartIx);
if (not hartPtr)
return false;
auto& hart = *hartPtr;
auto pacPtr = checkTag("execute", hartIx, tag);
if (not pacPtr)
return false;
auto& packet = *pacPtr;
auto& di = packet.decodedInst();
if (di.isLr())
return true; // LR is executed and retired at PerApi::retire.
auto& packetMap = hartPacketMaps_.at(hartIx);
if (packet.executed())
{
// Instruction is being re-executed. Must be load/store. Every instruction that
// depends on it must be re-executed.
if (not di.isLoad() and not di.isStore())
assert(0);
auto iter = packetMap.find(packet.tag());
assert(iter != packetMap.end());
for ( ; iter != packetMap.end(); ++iter)
{
auto succ = iter->second; // Successor packet
if (succ->dependsOn(packet))
succ->executed_ = false;
}
}
// Collect register operand values.
bool peekOk = true;
assert(di.operandCount() <= packet.opVal_.size());
for (unsigned i = 0; i < di.operandCount(); ++i)
{
if (di.ithOperandType(i) == WdRiscv::OperandType::Imm)
{
packet.opVal_.at(i) = di.ithOperand(i);
continue;
}
assert(di.ithOperandMode(i) != WdRiscv::OperandMode::None);
unsigned regNum = di.ithOperand(i);
unsigned gri = globalRegIx(di.ithOperandType(i), regNum);
uint64_t value = 0;
auto& producer = packet.opProducers_.at(i);
if (producer)
{
value = getDestValue(*producer, gri);
if (not producer->executed())
{
std::cerr << "Error: PerfApi::execute: Hart-ix=" << hartIx << "tag=" << tag
<< " depends on tag=" << producer->tag_ << " which is not yet executed.\n";
assert(0);
return false;
}
}
else
peekOk = peekRegister(hart, di.ithOperandType(i), regNum, value) and peekOk;
packet.opVal_.at(i) = value;
}
// Execute the instruction: Poke source register values, execute, recover destination
// values.
if (not execute(hartIx, packet))
assert(0);
if (not peekOk)
assert(packet.trap_);
packet.executed_ = true;
packet.execTime_ = time;
if (packet.predicted_)
packet.mispredicted_ = packet.prTarget_ != packet.nextIva_;
if (packet.isBranch())
{
// Check if the next instruction in program order is at the right PC.
auto iter = packetMap.find(packet.tag());
++iter;
if (iter != packetMap.end())
{
auto& next = *(iter->second);
if (next.iva_ != packet.nextIva_)
{
next.shouldFlush_ = true;
next.flushVa_ = packet.nextIva_;
}
if (next.executed_)
{
packet.shouldFlush_ = true;
packet.flushVa_ = packet.iva_;
}
}
}
return true;
}
bool
PerfApi::execute(unsigned hartIx, InstrPac& packet)
{
assert(packet.decoded());
auto hartPtr = getHart(hartIx);
assert(hartPtr);
auto& hart = *hartPtr;
uint64_t prevPc = hart.peekPc();
uint64_t prevInstrCount = hart.getInstructionCount();
hart.pokePc(packet.instrVa());
hart.setInstructionCount(packet.tag_ - 1);
std::array<uint64_t, 4> prevVal; // Previous operand values
// Save hart register values corresponding to packet operands in prevVal.
bool saveOk = saveHartValues(hart, packet, prevVal);
// Install packet operand values (some obtained from previous in-flight instructions)
// into the hart registers.
bool setOk = setHartValues(hart, packet);
assert(packet.tag_ > hartLastRetired_.at(hartIx));
hart.adjustTime(packet.tag_ - hartLastRetired_.at(hartIx) - 1);
auto& di = packet.decodedInst();
unsigned imsicId = 0, imsicGuest = 0;
if (di.isCsr())
saveImsicTopei(hart, CSRN(di.ithOperand(2)), imsicId, imsicGuest);
// Execute
skipIoLoad_ = true; // Load from IO space takes effect at retire.
hart.singleStep();
skipIoLoad_ = false;
bool trap = hart.lastInstructionTrapped();
packet.trap_ = packet.trap_ or trap;
// If save fails or set fails, there must be a trap.
if (not saveOk or not setOk)
assert(trap);
// Record PC of subsequent packet.
packet.nextIva_ = hart.peekPc();
if (not trap)
recordExecutionResults(hart, packet);
// Undo changes to the hart.
hart.adjustTime(-(int64_t)(packet.tag_ - hartLastRetired_.at(hartIx))); // Restore timer value.
// Restore CSRs modified by the instruction or trap. TODO: For vector ld/st we have to
// restore partially modified vectors.
if (di.isXRet() and not trap)
{ // For an MRET/SRET/... Privilege may have been lowered. Restore it before restoring CSRs.
hart.setVirtualMode(hart.lastVirtMode());
hart.setPrivilegeMode(hart.lastPrivMode());
}
// Restore changed CSR changes due to a trap or to mret/sret.
if (trap or di.isXRet())
{
std::vector<CSRN> csrns;
hart.lastCsr(csrns);
for (auto csrn : csrns)
{
uint64_t value = hart.lastCsrValue(csrn);
if (not hart.pokeCsr(csrn, value))
assert(0);
}
}
if (trap)
{ // Privilege raised. Restore it after restoring CSRs.
hart.setVirtualMode(hart.lastVirtMode());
hart.setPrivilegeMode(hart.lastPrivMode());
}
// Restore hart registers that we changed before single step.
restoreHartValues(hart, packet, prevVal);
if (di.isCsr())
restoreImsicTopei(hart, CSRN(di.ithOperand(2)), imsicId, imsicGuest);
hart.setTargetProgramFinished(false);
hart.pokePc(prevPc);
hart.setInstructionCount(prevInstrCount);
hart.clearTraceData();
return true;
}
bool
PerfApi::retire(unsigned hartIx, uint64_t time, uint64_t tag)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_retire %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Retire", time))
return false;
auto hart = checkHart("Retire", hartIx);
if (not hart)
return false;
auto pacPtr = checkTag("Retire", hartIx, tag);
if (not pacPtr)
return false;
auto& packet = *pacPtr;
if (tag <= hartLastRetired_.at(hartIx))
{
std::cerr << "Hart=" << hartIx << " time=" << time << " tag=" << tag
<< " Out of order retire\n";
return false;
}
hartLastRetired_.at(hartIx) = tag;
if (packet.retired())
{
std::cerr << "Hart=" << hartIx << " time=" << time << " tag=" << tag
<< " Tag retired more than once\n";
return false;
}
if (packet.instrVa() != hart->peekPc())
{
std::cerr << "Hart=" << hartIx << " time=" << time << " tag=" << tag << std::hex
<< " Wrong pc at retire: 0x" << packet.instrVa() << " expecting 0x"
<< hart->peekPc() << '\n' << std::dec;
return false;
}
hart->setInstructionCount(tag - 1);
hart->singleStep(traceFiles_.at(hartIx));
// Undo renaming of destination registers.
auto& producers = hartRegProducers_.at(hartIx);
auto& di = packet.decodedInst();
for (size_t i = 0; i < di.operandCount(); ++i)
{
using OM = WdRiscv::OperandMode;
auto mode = di.ithOperandMode(i);
if (mode == OM::Write or mode == OM::ReadWrite)
{
unsigned regNum = di.ithOperand(i);
unsigned gri = globalRegIx(di.ithOperandType(i), regNum);
auto& producer = producers.at(gri);
if (producer and producer->tag() == packet.tag())
producer = nullptr;
}
}
if (di.isLr())
{
bool trap = hart->lastInstructionTrapped();
packet.trap_ = packet.trap_ or trap;
// Record PC of subsequent packet.
packet.nextIva_ = hart->peekPc();
if (not trap)
recordExecutionResults(*hart, packet);
packet.executed_ = true;
}
packet.retired_ = true;
if (packet.isAmo() or packet.isSc())
{
uint64_t sva = 0, spa1 = 0, spa2 = 0, sval = 0;
unsigned size = hart->lastStore(sva, spa1, spa2, sval);
if (size != 0) // Could be zero for a failed sc
if (not commitMemoryWrite(*hart, spa1, size, packet.storeData_))
assert(0);
if (packet.isSc())
hart->cancelLr(WdRiscv::CancelLrCause::SC);
auto& storeMap = hartStoreMaps_.at(hartIx);
packet.drained_ = true;
storeMap.erase(packet.tag());
}
// Clear dependency on other packets to expedite release of packet memory.
for (auto& producer : packet.opProducers_)
producer = nullptr;
// Stores erased at drain time.
if (not packet.isStore())
{
auto& packetMap = hartPacketMaps_.at(hartIx);
packetMap.erase(packet.tag());
}
return true;
}
WdRiscv::ExceptionCause
PerfApi::translateInstrAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa)
{
auto hart = checkHart("Translate-instr-addr", hartIx);
hart->clearPageTableWalk();
bool r = false, w = false, x = true;
auto pm = hart->privilegeMode();
return hart->transAddrNoUpdate(iva, pm, hart->virtMode(), r, w, x, ipa);
}
WdRiscv::ExceptionCause
PerfApi::translateLoadAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa)
{
auto hart = checkHart("translate-load-addr", hartIx);
hart->clearPageTableWalk();
bool r = true, w = false, x = false;
auto pm = hart->privilegeMode();
return hart->transAddrNoUpdate(iva, pm, hart->virtMode(), r, w, x, ipa);
}
WdRiscv::ExceptionCause
PerfApi::translateStoreAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa)
{
auto hart = checkHart("translate-store-addr", hartIx);
hart->clearPageTableWalk();
bool r = false, w = true, x = false;
auto pm = hart->privilegeMode();
return hart->transAddrNoUpdate(iva, pm, hart->virtMode(), r, w, x, ipa);
}
WdRiscv::ExceptionCause
PerfApi::translateInstrAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa,
std::vector<std::vector<WalkEntry>>& walks)
{
auto hart = checkHart("translate-instr-addr", hartIx);
auto virtmem = hart->virtMem();
auto prevTrace = virtmem.enableTrace(true);
auto ec = translateInstrAddr(hartIx, iva, ipa);
virtmem.enableTrace(prevTrace);
walks = hart->virtMem().getFetchWalks();
return ec;
}
WdRiscv::ExceptionCause
PerfApi::translateLoadAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa,
std::vector<std::vector<WalkEntry>>& walks)
{
auto hart = checkHart("translate-load-addr", hartIx);
auto virtmem = hart->virtMem();
auto prevTrace = virtmem.enableTrace(true);
auto ec = translateLoadAddr(hartIx, iva, ipa);
virtmem.enableTrace(prevTrace);
walks = hart->virtMem().getDataWalks();
return ec;
}
WdRiscv::ExceptionCause
PerfApi::translateStoreAddr(unsigned hartIx, uint64_t iva, uint64_t& ipa,
std::vector<std::vector<WalkEntry>>& walks)
{
auto hart = checkHart("translate-store-addr", hartIx);
auto virtmem = hart->virtMem();
auto prevTrace = virtmem.enableTrace(true);
auto ec = translateStoreAddr(hartIx, iva, ipa);
virtmem.enableTrace(prevTrace);
walks = hart->virtMem().getDataWalks();
return ec;
}
bool
PerfApi::drainStore(unsigned hartIx, uint64_t time, uint64_t tag)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_drain_store %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Drain-store", time))
return false;
auto hart = checkHart("Drain-store", hartIx);
auto pacPtr = checkTag("Drain-store", hartIx, tag);
if (not hart or not pacPtr or not pacPtr->retired())
{
assert(0);
return false;
}
auto& packet = *pacPtr;
if (not packet.di_.isStore())
{
std::cerr << "Hart=" << hartIx << " time=" << time << " tag=" << tag
<< " Draining a non-store instruction\n";
return false;
}
if (packet.isAmo() or packet.isSc())
assert(packet.drained()); // AMO/SC drained at retire.
else
{
if (packet.drained())
{
std::cerr << "Hart=" << hartIx << " time=" << time << " tag=" << tag
<< " Instruction drained more than once\n";
assert(0);
}
uint64_t value = packet.storeData_;
uint64_t addr = packet.dpa_; // FIX TODO : Handle page crossing store.
if (packet.dsize_ and not commitMemoryWrite(*hart, addr, packet.dsize_, value))
assert(0);
packet.drained_ = true;
}
// Clear dependency on other packets to expedite release of packet memory.
for (auto& producer : packet.opProducers_)
producer = nullptr;
auto& packetMap = hartPacketMaps_.at(hartIx);
packetMap.erase(packet.tag());
auto& storeMap = hartStoreMaps_.at(hartIx);
storeMap.erase(packet.tag());
return true;
}
bool
PerfApi::getLoadData(unsigned hartIx, uint64_t tag, uint64_t va, uint64_t pa1,
uint64_t pa2, unsigned size, uint64_t& data)
{
auto hart = checkHart("Get-load-data", hartIx);
auto packet = checkTag("Get-load-Data", hartIx, tag);
bool isLoad = packet->di_.isLoad() or packet->di_.isAmo();
if (not hart or not packet or not isLoad or packet->trapped())
{
assert(0);
return false;
}
// If AMO destination register is x0, we lose the loaded value: redo the read for AMOs
// to avoid that case. AMOs should not have a discrepancy between early read and read at
// excecute, so redoing the read is ok.
if (packet->executed() and not packet->isAmo())
{
assert(size == packet->dataSize());
data = packet->destValues_.at(0).second;
return true;
}
data = 0;
if (hart->isDeviceAddr(pa1))
{
if (skipIoLoad_)
return true; // Load from IO space happens at execute.
hart->deviceRead(pa1, size, data);
return true;
}
if (uint64_t toHost = 0; hart->getToHostAddress(toHost) && toHost == pa1)
return true; // Reading from toHost yields 0.
auto& storeMap = hartStoreMaps_.at(hartIx);
unsigned mask = (1 << size) - 1; // One bit ber byte of load data.
unsigned forwarded = 0; // One bit per forwarded byte.
for (auto& kv : storeMap)
{
auto stTag = kv.first;
auto& stPac = kv.second;
if (stTag > tag)
break;
if (not stPac->executed())
continue;
uint64_t stAddr = stPac->dataVa();
unsigned stSize = stPac->dataSize();
if (stAddr + stSize < va or va + size < stAddr)
continue; // No overlap.
uint64_t stData = stPac->opVal_.at(0);
for (unsigned i = 0; i < size; ++i)
{
unsigned byteMask = 1 << i;
uint64_t byteAddr = va + i;
if (byteAddr >= stAddr and byteAddr < stAddr + stSize)
{
data &= ~(0xffull << (i * 8));
uint64_t stByte = (stData >> (byteAddr - stAddr)*8) & 0xff;
data |= stByte << (i*8);
forwarded |= byteMask;
}
}
}
if (forwarded == mask)
return true;
unsigned size1 = size;
if (pa1 != pa2 and pageNum(pa1) != pageNum(pa2))
size1 = offsetToNextPage(pa1);
for (unsigned i = 0; i < size; ++i)
if (not (forwarded & (1 << i)))
{
uint8_t byte = 0;
if (i < size1)
{
if (not hart->peekMemory(pa1 + i, byte, true))
assert(0);
}
else
{
if (not hart->peekMemory(pa2 + (i-size1), byte, true))
assert(0);
}
data |= uint64_t(byte) << (i*8);
}
return true;
}
bool
PerfApi::setStoreData(unsigned hartIx, uint64_t tag, uint64_t value)
{
auto hart = checkHart("Set-store-data", hartIx);
auto packetPtr = checkTag("Set-store-Data", hartIx, tag);
if (not packetPtr)
{
assert(0);
return false;
}
auto& packet = *packetPtr;
if (not hart or not (packet.isStore() or packet.isAmo()))
{
assert(0);
return false;
}
packet.storeData_ = value;
return true;
}
bool
PerfApi::commitMemoryWrite(Hart64& hart, uint64_t addr, unsigned size, uint64_t value)
{
if (hart.isToHostAddr(addr))
{
hart.handleStoreToHost(addr, value);
return true;
}
switch (size)
{
case 1: return hart.pokeMemory(addr, uint8_t(value), true);
case 2: return hart.pokeMemory(addr, uint16_t(value), true);
case 4: return hart.pokeMemory(addr, uint32_t(value), true);
case 8: return hart.pokeMemory(addr, value, true);
default: assert(0);
}
return false;
}
bool
PerfApi::flush(unsigned hartIx, uint64_t time, uint64_t tag)
{
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_flush %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Flush", time))
return false;
if (not checkHart("Flush", hartIx))
return false;
auto& packetMap = hartPacketMaps_.at(hartIx);
auto& storeMap = hartStoreMaps_.at(hartIx);
auto& producers = hartRegProducers_.at(hartIx);
// Flush tag and all older packets. Flush in reverse order to undo register renaming.
for (auto iter = packetMap.rbegin(); iter != packetMap.rend(); )
{
auto pacPtr = iter->second;
if (pacPtr->tag_ < tag)
break;
if (not pacPtr or pacPtr->retired())
{
assert(0);
return false;
}
auto& packet = *pacPtr;
auto& di = packet.di_;
for (size_t i = 0; i < di.operandCount(); ++i)
{
auto mode = di.effectiveIthOperandMode(i);
if (mode == WdRiscv::OperandMode::Write or
mode == WdRiscv::OperandMode::ReadWrite)
{
unsigned regNum = di.ithOperand(i);
unsigned gri = globalRegIx(di.ithOperandType(i), regNum);
if (gri != 0)
assert(producers.at(gri)->tag_ == packet.tag_);
auto prev = packet.opProducers_.at(i);
if (prev and prev->retired_)
prev = nullptr;
producers.at(gri) = prev;
}
}
++iter;
}
// delete input tag and all newer instructions
std::erase_if(packetMap, [&tag](const auto &packet)
{
auto const& [_, pacPtr] = packet;
return pacPtr->tag_ >= tag;
});
std::erase_if(storeMap, [&tag](const auto &packet)
{
auto const& [_, pacPtr] = packet;
return pacPtr->tag_ >= tag;
});
if (prevFetch_ && prevFetch_->tag_ > tag)
prevFetch_ = nullptr;
return true;
}
bool
PerfApi::shouldFlush(unsigned hartIx, uint64_t time, uint64_t tag, bool& flush,
uint64_t& addr)
{
flush = false;
addr = 0;
if (commandLog_)
fprintf(commandLog_, "hart=%" PRIu32 " time=%" PRIu64 " perf_model_should_flush %" PRIu64 "\n",
hartIx, time, tag);
if (not checkTime("Flush", time))
return false;
if (not checkHart("Flush", hartIx))
return false;
auto pacPtr = checkTag("Retire", hartIx, tag);
if (not pacPtr)
return false;
auto& packet = *pacPtr;
if (packet.shouldFlush())
{
flush = true;
addr = packet.flushVa_;
}
else
{
// If on the wrong path after a branch, then we wshould flush.
auto& packetMap = hartPacketMaps_.at(hartIx);
auto iter = packetMap.find(tag); --iter;
for ( ; iter != packetMap.end(); --iter)
{
auto& packet = *iter->second;
if (packet.mispredicted_)
{
flush = true;
if (packet.di_.isBranch())
addr = packet.nextIva_;
else
addr = packet.iva_;
}
}
}
return true;
}
unsigned
InstrPac::getSourceOperands(std::array<Operand, 3>& ops)
{
assert(decoded_);
if (not decoded_)
return 0;
unsigned count = 0;
using OM = WdRiscv::OperandMode;
for (unsigned i = 0; i < di_.operandCount(); ++i)
{
if (di_.ithOperandMode(i) == OM::Read or di_.ithOperandMode(i) == OM::ReadWrite or di_.ithOperandType(i) == OperandType::Imm)
{
auto& op = ops.at(count);
op.type = di_.ithOperandType(i);
op.number = (di_.ithOperandType(i) == OperandType::Imm) ? 0 : di_.ithOperand(i);
op.value = opVal_.at(i);
++count;
}
}
return count;
}
unsigned
InstrPac::getDestOperands(std::array<Operand, 2>& ops)
{
assert(decoded_);
if (not decoded_)
return 0;
unsigned count = 0;
using OM = WdRiscv::OperandMode;
for (unsigned i = 0; i < di_.operandCount(); ++i)
{
auto mode = di_.effectiveIthOperandMode(i);
if (mode == OM::Write or mode == OM::ReadWrite)
{
auto& op = ops.at(count);
op.type = di_.ithOperandType(i);