2005
Thermal-aware mapping and placement for 3-D NoC designs 29 A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC 12 Novel 7T sram cell for low power cache design 14
2006
3-D Topologies for Networks-on-Chip 17 Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping 9 Platform-Based Behavior-Level and System-Level Synthesis 18
2007
An independent-gate FinFET SRAM cell for high data stability and enhanced integration density 13 A prototype of a wireless-based test system 6 A 45nm dual-port SRAM with write and read capability enhancement at low voltage 20
2008
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards 8 A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies 8 65NM sub-threshold 11T-SRAM for ultra low voltage applications 8
2009
A high-level compilation toolchain for heterogeneous systems 8 A flow regulator for On-Chip Communication 9 Generic integer linear programming formulation for 3D IC partitioning 11
2010
2011
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design 11 Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems 5 Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip 7
2012
Variation-and-aging aware low power embedded SRAM for multimedia applications 3 SOLARCAP: Super capacitor buffering of solar energy for self-sustainable field systems 4 Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme 3
2013
UWB receiver for breast cancer detection: Comparison between two different approaches 1 An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder 1 Light field data processor design for depth estimation using confidence-assisted disparities 1
2014
Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation 1 CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 cores 1 DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level 1