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exec.pas
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{ HD61700 instruction execution }
unit Exec;
interface
procedure IllComm;
procedure Ld_02;
procedure AdSb_08;
procedure AdbSbb_0A;
procedure Logic_0C;
procedure St_10;
procedure Ld_11;
procedure Stl_12;
procedure Ldl_13;
procedure PpoPfl_14;
procedure Psr_15;
procedure Pst_16;
procedure Rod_18;
procedure Rou_18;
procedure Bid_18;
procedure Biu_18;
procedure Did_1A;
procedure Diu_1A;
procedure BydByu_1A;
procedure CmpInv_1B;
procedure GpoGfl_1C;
procedure Gsr_1D;
procedure Gst_1E;
procedure StSti_20;
procedure Std_24;
procedure PhsPhu_26;
procedure LdLdi_28;
procedure Ldd_2C;
procedure PpsPpu_2E;
procedure Jp_3x;
procedure Ld_42;
procedure AdSb_38;
procedure St_50;
procedure Ld_51;
procedure Stl_52;
procedure BupsBdns_58;
procedure SupSdn_5C;
procedure Cal_7x;
procedure Ldw_82;
procedure AdwSbw_88;
procedure AdbwSbbw_8A;
procedure LogicW_8C;
procedure Stw_90;
procedure Ldw_91;
procedure Stlw_92;
procedure Ldlw_93;
procedure Pre_96;
procedure Rodw_98;
procedure Rouw_98;
procedure Bidw_98;
procedure Biuw_98;
procedure Didw_9A;
procedure Diuw_9A;
procedure Bydw_9A;
procedure Byuw_9A;
procedure CmpwInvw_9B;
procedure GpowGflw_9C;
procedure Gre_9E;
procedure StwStiw_A0;
procedure Stdw_A4;
procedure PhswPhuw_A6;
procedure LdwLdiw_A8;
procedure Lddw_AC;
procedure PpswPpuw_AE;
procedure Jr_Bx;
procedure AdwSbw_B8;
procedure Ldm_C2;
procedure AdbmSbbm_C8;
procedure AdbmSbbm_CA;
procedure LogicM_CC;
procedure Stw_D0;
procedure Ldw_D1;
procedure Stlm_D2;
procedure Ldlm_D3;
procedure Pre_D6;
procedure BupBdn_D8;
procedure Didm_DA;
procedure Dium_DA;
procedure Bydm_DA;
procedure Byum_DA;
procedure CmpmInvm_DB;
procedure Jp_DE;
procedure Jp_DF;
procedure StmStim_E0;
procedure Stdm_E4;
procedure PhsmPhum_E6;
procedure LdmLdim_E8;
procedure Lddm_EC;
procedure PpsmPpum_EE;
procedure Rtn_Fx;
procedure Nop_F8;
procedure Clt_F9;
procedure Fst_FA;
procedure Slw_FB;
procedure Cani_FC;
procedure Rtni_FD;
procedure Off_FE;
procedure Trp_FF;
{ serial port extra }
procedure SerialPoll;
implementation
uses Def, Keyboard, Lcd, Port, Serial;
type
Func2 = function : boolean;
Func3 = function (x1: byte; x2: byte) : byte;
var
ky1: word; { used to prevent the KY register write }
const
{ 8-bit registers, access to the r8tab[6] entry is illegal }
r8tab: array[0..7] of pointer =
( @pe, @pd, @ib, @ua, @ia, @ie, @tm, @tm );
{ 16-bit registers }
r16tab: array[0..7] of pointer =
( @ix, @iy, @iz, @us, @ss, @ky1, @ky1, @ky1 );
{ specific index registers, access to the last entry is illegal }
sirtab: array[0..3] of pointer = ( @sx, @sy, @sz, @sz );
{ stack pointers }
stacktab: array[0..1] of pointer = ( @ss, @us );
{ 8-bit BCD addition }
function AddBcd (addend1: cardinal; addend2: cardinal) : cardinal;
begin
Result := (addend1 and $0F) + (addend2 and $0F);
if Result > $09 then Result := ((Result + $06) and $0F) or $10;
if Result > $1F then Dec(Result,$10);
Inc(Result, (addend1 and $F0) + (addend2 and $F0));
if Result > $9F then Result := ((Result + $60) and $FF) or $100;
end {AddBcd};
{ 8-bit BCD subtraction }
function SubBcd (minuend: cardinal; subtrahend: cardinal) : cardinal;
begin
Result := (minuend and $0F) - (subtrahend and $0F);
if Result > $09 then Result := (Result - $06) or cardinal (-$10);
Inc(Result, (minuend and $F0) - (subtrahend and $F0));
if Result > $9F then Result := (Result - $60) or cardinal (-$100);
end {SubBcd};
procedure SetFlagsB (x: byte);
begin
flag := flag and not (Z_bit or C_bit or UZ_bit or LZ_bit);
if x <> 0 then flag := flag or Z_bit;
if (x and $0F) <> 0 then flag := flag or LZ_bit;
if (x and $F0) <> 0 then flag := flag or UZ_bit;
end {SetFlagsB};
procedure SetFlagsW (x: word);
begin
flag := flag and not (Z_bit or C_bit or UZ_bit or LZ_bit);
if x <> 0 then flag := flag or Z_bit;
if (x and $0F00) <> 0 then flag := flag or LZ_bit;
if (x and $F000) <> 0 then flag := flag or UZ_bit;
end {SetFlagsW};
procedure SetFlagsD (x: word);
begin
flag := flag and not (Z_bit or C_bit or UZ_bit or LZ_bit);
if x <> 0 then flag := flag or Z_bit;
if (x and $000F) <> 0 then flag := flag or LZ_bit;
if (x and $00F0) <> 0 then flag := flag or UZ_bit;
end {SetFlagsW};
procedure SetFlagsM (x: byte);
begin
flag := flag and not (Z_bit or C_bit or UZ_bit or LZ_bit);
if (x and $0F) <> 0 then flag := flag or LZ_bit;
if (x and $F0) <> 0 then flag := flag or UZ_bit;
end {SetFlagsM};
{ set the Carry flag for the NA and OR instructions }
procedure SetLogicC;
var
x: byte;
begin
x := opcode[0] and 3;
if (x = 1) or (x = 2) then flag := flag or C_bit;
end {SetLogicC};
function Imm3Arg (x: byte): byte;
begin
Result := ((x shr 5) and 7) + 1;
if Result < 2 then Result := 2;
end {Imm3Arg};
function Imm7Arg : word;
var
x, y: word;
begin
y := pc;
if (opforg > 0) and not Odd(opindex) then FetchByte;
x := FetchByte;
if (x and $80) <> 0 then x := $80 - x;
Imm7Arg := x + y;
end {Imm7Arg};
function AbsArg : word;
var
x: word;
begin
x := FetchByte;
if opforg > 0 then FetchByte;
AbsArg := x or (FetchByte shl 8);
end {AbsArg};
function RegArg (x: byte) : byte;
begin
RegArg := x and $1F;
end {RegArg};
function SirArg (x: byte) : pointer;
begin
SirArg := sirtab[(x shr 5) and 3];
end {SirArg};
function ShortRegArg (x: byte) : byte;
begin
if (x and $60) = $60 then ShortRegArg := RegArg(FetchByte)
else ShortRegArg := RegArg(ptrb(SirArg(x))^);
end {ShortRegArg};
function ShortRegAr1 (x, y: byte) : byte;
begin
if (x and $60) = $60 then ShortRegAr1 := RegArg(y)
else ShortRegAr1 := RegArg(ptrb(SirArg(x))^);
end {ShortRegAr1};
function ShortRegImm8 (x: byte) : byte;
begin
if (opcode[0] and $40) = 0 then
ShortRegImm8 := mr[ShortRegArg(x)]
else
ShortRegImm8 := FetchByte;
end {ShortRegImm8};
function IndexOffset (x: byte) : word;
begin
if (opcode[0] and $40) = 0 then
Result := word(mr[ShortRegArg(x)])
else
Result := word(FetchByte);
if (x and $80) <> 0 then Result := -Result;
end {IndexOffset};
function GetRegPair (x: byte) : word;
begin
GetRegPair := mr[RegArg(x)] or (mr[RegArg(x+1)] shl 8);
end {GetRegPair};
procedure PutRegPair (x: byte; y: word);
begin
mr[RegArg(x)] := Lo(y);
mr[RegArg(x+1)] := Hi(y);
end {PutRegPair};
{ transfer a byte (two nibbles) through the LCD port }
function LcdByte (x: byte) : byte;
begin
Result := LcdTransfer (x);
Result := Result or (LcdTransfer (x shr 4) shl 4);
end {LcdByte};
{ condition codes evaluation }
function CC_z : boolean;
begin
CC_z := (flag and Z_bit) = 0;
end {CC_z};
function CC_nc : boolean;
begin
CC_nc := (flag and C_bit) = 0;
end {CC_nc};
function CC_lz : boolean;
begin
CC_lz := (flag and LZ_bit) = 0;
end {CC_lz};
function CC_uz : boolean;
begin
CC_uz := (flag and UZ_bit) = 0;
end {CC_uz};
function CC_nz : boolean;
begin
CC_nz := (flag and Z_bit) <> 0;
end {CC_nz};
function CC_c : boolean;
begin
CC_c := (flag and C_bit) <> 0;
end {CC_c};
function CC_nlz : boolean;
begin
CC_nlz := (flag and LZ_bit) <> 0;
end {CC_nlz};
function CC_none : boolean;
begin
CC_none := True;
end {CC_none};
function TestCC : boolean;
const dtab: array[0..7] of pointer = (
@CC_z, { Z }
@CC_nc, { NC }
@CC_lz, { LZ }
@CC_uz, { UZ }
@CC_nz, { NZ }
@CC_c, { C }
@CC_nlz, { NLZ }
@CC_none ); { unconditional }
begin
TestCC := Func2(dtab[opcode[0] and 7]);
end {TestCC};
procedure Push (where: pointer; what: byte);
begin
Dec (ptrw(where)^);
DstPtr (Addr18 (ua shr 2, ptrw(where)^))^ := what;
end {Push};
function Pop (from: pointer) : byte;
begin
Pop := SrcPtr (Addr18 (ua shr 2, ptrw(from)^))^;
Inc (ptrw(from)^);
end {Push};
procedure OptionalJr (x: byte);
begin
if (x and $80) <> 0 then
begin
pc := Imm7Arg;
opindex := 0; { prevents subsequent PC alignment }
end {if};
end {OptionalJr};
function AnOp (x1: byte; x2: byte) : byte;
begin
AnOp := x1 and x2;
end {AnOp};
function NaOp (x1: byte; x2: byte) : byte;
begin
NaOp := not (x1 and x2);
end {NaOp};
function OrOp (x1: byte; x2: byte) : byte;
begin
OrOp := x1 or x2;
end {OrOp};
function XrOp (x1: byte; x2: byte) : byte;
begin
XrOp := x1 xor x2;
end {XrOp};
function LogicOp (x1: byte; x2: byte) : byte;
const
dtab: array[0..3] of pointer = (@AnOp, @NaOp, @OrOp, @XrOp);
begin
LogicOp := Func3 (dtab[opcode[0] and 3]) (x1, x2);
end {LogicOp};
procedure IllComm;
begin
Inc (cycles, 3);
end {Illcomm};
procedure Ld_02;
var
x: byte;
begin
x := FetchByte;
mr[RegArg(x)] := mr[ShortRegArg(x)];
OptionalJr(x);
Inc (cycles, 3);
end {Ld_02};
procedure AdSb_08;
var
x, src, dst: byte;
y: word;
begin
x := FetchByte;
dst := RegArg(x);
src := ShortRegImm8(x);
if (opcode[0] and 1) = 0 then
y := word(mr[dst]) + word(src)
else
y := word(mr[dst]) - word(src);
if (opcode[0] and 8) <> 0 then mr[dst] := byte(y);
SetFlagsB(byte(y));
if y > $FF then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {AdSb_08};
procedure AdbSbb_0A;
var
x, src, dst: byte;
y: cardinal;
begin
x := FetchByte;
dst := RegArg(x);
src := ShortRegImm8(x);
if (opcode[0] and 1) = 0 then
y := AddBcd (cardinal(mr[dst]), cardinal(src))
else
y := SubBcd (cardinal(mr[dst]), cardinal(src));
mr[dst] := byte(y);
SetFlagsB(byte(y));
if y > $FF then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {AdbSbb_0A};
procedure Logic_0C;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := LogicOp (mr[dst], ShortRegImm8(x));
if (opcode[0] and 8) <> 0 then mr[dst] := y;
SetFlagsB(byte(y));
SetLogicC;
OptionalJr(x);
Inc (cycles, 3);
end {Logic_0C};
procedure St_10;
var
x: byte;
o: word;
begin
x := FetchByte;
o := GetRegPair (ShortRegArg(x));
DstPtr(Addr18(ua shr 4,o))^ := mr[RegArg(x)];
OptionalJr(x);
Inc (cycles, 8);
end {St_10};
procedure Ld_11;
var
x: byte;
o: word;
begin
x := FetchByte;
o := GetRegPair (ShortRegArg(x));
mr[RegArg(x)] := SrcPtr(Addr18(ua shr 4,o))^;
OptionalJr(x);
Inc (cycles, 8);
end {Ld_11};
procedure Stl_12;
var
x: byte;
begin
x := FetchByte;
LcdSync;
LcdByte (mr[RegArg(x)]);
OptionalJr(x);
Inc (cycles, 11);
end {Stl_12};
procedure Ldl_13;
var
x: byte;
begin
x := FetchByte;
LcdSync;
mr[RegArg(x)] := LcdByte (0);
OptionalJr(x);
Inc (cycles, 11);
end {Ldl_13};
procedure PpoPfl_14;
var
x, y: byte;
begin
x := FetchByte;
if (opcode[0] and $40) = 0 then
y := mr[RegArg(x)]
else
y := FetchByte;
if (x and $40) = 0 then
lcdctrl := y
else
flag := (flag and $0F) or (y and $F0);
if (opcode[0] and $40) = 0 then OptionalJr(x);
Inc (cycles, 3);
end {PpoPfl_14};
procedure Psr_15;
var
x, y: byte;
begin
x := FetchByte;
if (opcode[0] and $40) = 0 then
y := mr[RegArg(x)]
else
y := x;
ptrb(SirArg(x))^ := y and $1F;
if (opcode[0] and $40) = 0 then OptionalJr(x);
Inc (cycles, 3);
end {Psr_15};
procedure Pst_16;
var
x, y, i: byte;
begin
x := FetchByte;
i := ((opcode[0] shl 2) and 4) + ((x shr 5) and 3);
if (opcode[0] and $40) = 0 then y := mr[RegArg(x)] else y := FetchByte;
if i = 2 then { IB }
ib := (ib and $1F) or (y and $E0)
else if i < 6 then { the TM register cannot be written }
ptrb(r8tab[i])^ := y;
if i <= 1 then WritePd { PE, PD }
else if i = 5 then { IE }
begin
y := y shr 3;
ib := ib and (y or $E0);
iserv := iserv and y;
{ HACK: Inform the serial port module that we have enabled or disabled INT1 }
SerialForm.PBOpened((y and INT1_bit) <> 0);
end {if};
if (opcode[0] and $40) = 0 then OptionalJr(x);
Inc (cycles, 3);
end {Pst_16};
procedure Rod_18;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := mr[dst];
mr[dst] := mr[dst] shr 1;
if (flag and C_bit) <> 0 then Inc (mr[dst], $80);
SetFlagsB(mr[dst]);
if (y and 1) <> 0 then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {Rod_18};
procedure Rou_18;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := mr[dst];
mr[dst] := mr[dst] shl 1;
if (flag and C_bit) <> 0 then Inc (mr[dst]);
SetFlagsB(mr[dst]);
if (y and $80) <> 0 then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {Rou_18};
procedure Bid_18;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := mr[dst];
mr[dst] := mr[dst] shr 1;
SetFlagsB(mr[dst]);
if (y and 1) <> 0 then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {Bid_18};
procedure Biu_18;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := mr[dst];
mr[dst] := mr[dst] shl 1;
SetFlagsB(mr[dst]);
if (y and $80) <> 0 then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {Biu_18};
procedure Did_1A;
var
x, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
mr[dst] := mr[dst] shr 4;
SetFlagsB(mr[dst]);
OptionalJr(x);
Inc (cycles, 3);
end {Did_1A};
procedure Diu_1A;
var
x, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
mr[dst] := mr[dst] shl 4;
SetFlagsB(mr[dst]);
OptionalJr(x);
Inc (cycles, 3);
end {Diu_1A};
procedure BydByu_1A;
var
x: byte;
begin
x := FetchByte;
mr[RegArg(x)] := 0;
flag := flag and not (C_bit or Z_bit or UZ_bit or LZ_bit);
OptionalJr(x);
Inc (cycles, 3);
end {BydByu_1A};
procedure CmpInv_1B;
var
x, y, dst: byte;
begin
x := FetchByte;
dst := RegArg(x);
y := not mr[dst];
if (x and $40) = 0 then Inc (y);
mr[dst] := y;
SetFlagsB(y);
if (y <> 0) or ((x and $40) <> 0) then flag := flag or C_bit;
OptionalJr(x);
Inc (cycles, 3);
end {CmpInv_1B};
procedure GpoGfl_1C;
var
x: byte;
begin
x := FetchByte;
if (x and $40) = 0 then
mr[RegArg(x)] := ReadPd
else
mr[RegArg(x)] := flag;
OptionalJr(x);
Inc (cycles, 3);
end {GpoGfl_1C};
procedure Gsr_1D;
var
x: byte;
begin
x := FetchByte;
mr[RegArg(x)] := ptrb(SirArg(x))^;
OptionalJr(x);
Inc (cycles, 3);
end {Gsr_1D};
procedure Gst_1E;
var
x, i: byte;
begin
x := FetchByte;
i := ((opcode[0] shl 2) and 4) + ((x shr 5) and 3);
mr[RegArg(x)] := ptrb(r8tab[i])^;
OptionalJr(x);
Inc (cycles, 3);
end {Gst_1E};
procedure StSti_20;
var
x, s: byte;
irsave: word;
ir: ptrw;
begin
if (opcode[0] and 1) = 0 then
begin
ir := ptrw(@ix);
s := ua shr 4;
end
else
begin
ir := ptrw(@iz);
s := ua shr 6;
end {if};
irsave := ir^;
x := FetchByte;
Inc (ir^, IndexOffset (x));
DstPtr(Addr18(s,ir^))^ := mr[RegArg(x)];
Inc (ir^);
if (opcode[0] and 2) = 0 then ir^ := irsave;
Inc (cycles, 8);
end {StSti_20};
procedure Std_24;
var
x, s: byte;
ir: ptrw;
begin
if (opcode[0] and 1) = 0 then
begin
ir := ptrw(@ix);
s := ua shr 4;
end
else
begin
ir := ptrw(@iz);
s := ua shr 6;
end {if};
x := FetchByte;
Inc (ir^, IndexOffset(x));
DstPtr(Addr18(s,ir^))^ := mr[RegArg(x)];
Inc (cycles, 6);
end {Std_24};
procedure PhsPhu_26;
begin
Push (stacktab[opcode[0] and 1], mr[RegArg(FetchByte)]);
Inc (cycles, 9);
end {PhsPhu_26};
procedure LdLdi_28;
var
x, s: byte;
irsave: word;
ir: ptrw;
begin
if (opcode[0] and 1) = 0 then
begin
ir := ptrw(@ix);
s := ua shr 4;
end
else
begin
ir := ptrw(@iz);
s := ua shr 6;
end {if};
irsave := ir^;
x := FetchByte;
Inc (ir^, IndexOffset(x));
mr[RegArg(x)] := SrcPtr(Addr18(s,ir^))^;
Inc (ir^);
if (opcode[0] and 2) = 0 then ir^ := irsave;
Inc (cycles, 8);
end {LdLdi_28};
procedure Ldd_2C;
var
x, s: byte;
ir: ptrw;
begin
if (opcode[0] and 1) = 0 then
begin
ir := ptrw(@ix);
s := ua shr 4;
end
else
begin
ir := ptrw(@iz);
s := ua shr 6;
end {if};
x := FetchByte;
Inc (ir^, IndexOffset(x));
mr[RegArg(x)] := SrcPtr(Addr18(s,ir^))^;
Inc (cycles, 6);
end {Ldd_2C};
procedure PpsPpu_2E;
begin
mr[RegArg(FetchByte)] := Pop (stacktab[opcode[0] and 1]);
Inc (cycles, 11);
end {PpsPpu_2E};
procedure Jp_3x;
var
x: word;
begin
x := AbsArg;
if TestCC then
begin
pc := x;
opindex := 0; { prevents subsequent PC alignment }
end {if};
Inc (cycles, 3);
end {Jp_3x};
procedure Ld_42;
var
x: byte;
begin
x := FetchByte;
mr[RegArg(x)] := FetchByte;
OptionalJr(x);
Inc (cycles, 3);
end {Ld_42};
procedure AdSb_38;
var
x, s: byte;
y, o: word;
src: ptrb;
begin
if (opcode[0] and 1) = 0 then
begin
o := ix;
s := ua shr 4;
end
else
begin
o := iz;
s := ua shr 6;
end {if};
x := FetchByte;
Inc (o, IndexOffset(x));
src := SrcPtr(Addr18(s,o));
if (opcode[0] and 2) = 0 then
y := word(src^) + word(mr[RegArg(x)])
else
y := word(src^) - word(mr[RegArg(x)]);
if (opcode[0] and 4) <> 0 then DstPtr(Addr18(s,o))^ := byte(y);
SetFlagsB(byte(y));
if y > $FF then flag := flag or C_bit;
Inc (cycles, 9);
end {AdSb_38};
procedure St_50;
var
x: byte;
o: word;
begin
x := FetchByte;
o := GetRegPair (ptrb(SirArg(x))^);
DstPtr(Addr18(ua shr 4,o))^ := FetchByte;
Inc (cycles, 8);
end {St_50};
procedure Ld_51;
var
x: byte;
begin
x := FetchByte;
mr[RegArg(x)] := FetchByte;
Inc (cycles, 8);
end {Ld_51};
procedure Stl_52;
begin
LcdSync;
LcdByte (FetchByte);
Inc (cycles, 12);
end {Stl_52};
procedure BupsBdns_58;
var
x1, x2, s1, s2: byte;
y, step: word;
begin
x1 := FetchByte;
s1 := ua shr 6;
s2 := ua shr 4;
if (opcode[0] and 1) = 0 then step := 1 else step := word(-1);
repeat
x2 := SrcPtr(Addr18(s2,ix))^;
DstPtr(Addr18(s1,iz))^ := x2;
y := word(x2) - word(x1);
Inc (cycles, 6);
if (y = 0) or (ix = iy) then Break;
Inc (ix, step);
Inc (iz, step);
until False;
SetFlagsB(byte(y));
if y > $FF then flag := flag or C_bit;
Inc (cycles, 3);
end {BupsBdns_58};
procedure SupSdn_5C;
var
x, s: byte;
y, step: word;
begin
x := FetchByte;
if (opcode[0] and $80) <> 0 then x := mr[RegArg(x)];
s := ua shr 4;
if (opcode[0] and 1) = 0 then step := 1 else step := word(-1);
repeat
y := word(SrcPtr(Addr18(s,ix))^) - word(x);
Inc (cycles, 6);
if (y = 0) or (ix = iy) then Break;
Inc (ix, step);
until False;
SetFlagsB(byte(y));
if y > $FF then flag := flag or C_bit;
Inc (cycles, 3);
end {SupSdn_5C};
procedure Cal_7x;
var
x: word;
begin
x := AbsArg;
if TestCC then
begin
Dec (pc);
Push (@ss, Hi (pc));
Push (@ss, Lo (pc));
pc := x;
opindex := 0; { prevents subsequent PC alignment }
Inc (cycles, 6);
end {if};
Inc (cycles, 3);
end {Cal_7x};