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builtin_op_importers.cpp
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/*
* SPDX-License-Identifier: Apache-2.0
*/
// Include assert.h prior to the below WAR to ensure that assert()
// definition obeys the NDEBUG define
#include <assert.h>
// Workaround for NDEBUG causing functional
// differences in ONNX / protobuf code on aarch64 platforms which leads
// to corruption.
#if defined(__aarch64__) && defined(__linux__) && defined(NDEBUG)
#undef NDEBUG
#define REDEFINE_NDEBUG
#endif
#include <onnx/onnx_pb.h>
#if defined(REDEFINE_NDEBUG)
#define NDEBUG
#undef REDEFINE_NDEBUG
#endif
#include "ConditionalHelpers.hpp"
#include "LoopHelpers.hpp"
#include "ModelImporter.hpp"
#include "NvInfer.h"
#include "NvInferPlugin.h"
#include "NvInferRuntime.h"
#include "OnnxAttrs.hpp"
#include "RNNHelpers.hpp"
#include "ShapeTensor.hpp"
#include "builtin_op_importers.hpp"
#include "half.h"
#include "onnx2trt_utils.hpp"
#include <algorithm> // For std::min, std::max
#include <array>
#include <cmath>
#include <cstring> // For std::memcpy, std::memset
#include <iostream>
#include <iterator>
#include <numeric> // For std::iota
#include <tuple>
#include <unordered_set>
namespace onnx2trt
{
string_map<NodeImporter>& getBuiltinOpImporterMap()
{
static string_map<NodeImporter> builtin_op_importers;
return builtin_op_importers;
}
namespace
{
using nvinfer1::DataType;
#define IGNORE_UNUSED_GLOBAL(x) \
static void _ignore_unused2_##x(); \
static void _ignore_unused1_##x() \
{ \
(void) _ignore_unused2_##x; \
(void) x; \
} \
static void _ignore_unused2_##x() \
{ \
(void) _ignore_unused1_##x; \
} \
struct SwallowSemicolon##x \
{ \
}
#define DECLARE_BUILTIN_OP_IMPORTER(op) \
NodeImportResult import##op( \
IImporterContext* ctx, ::ONNX_NAMESPACE::NodeProto const& node, std::vector<TensorOrWeights>& inputs)
#define DEFINE_BUILTIN_OP_IMPORTER(op) \
NodeImportResult import##op( \
IImporterContext* ctx, ::ONNX_NAMESPACE::NodeProto const& node, std::vector<TensorOrWeights>& inputs); \
static bool const op##_registered_builtin_op = registerBuiltinOpImporter(#op, import##op); \
IGNORE_UNUSED_GLOBAL(op##_registered_builtin_op); \
NodeImportResult import##op( \
IImporterContext* ctx, ::ONNX_NAMESPACE::NodeProto const& node, std::vector<TensorOrWeights>& inputs)
#define RETURN_FIRST_OUTPUT(layer) \
do \
{ \
nvinfer1::ILayer* layer_ptr = layer; \
ASSERT(layer_ptr && "Input layer is null.", ErrorCode::kUNSUPPORTED_NODE); \
return {{layer_ptr->getOutput(0)}}; \
} while (0)
#define RETURN_IDENTITY(input) \
do \
{ \
TensorOrWeights output = identity(ctx, input); \
ASSERT(output && "Failed to add an identity layer.", ErrorCode::kUNSUPPORTED_NODE); \
return {{output}}; \
} while (0)
#define RETURN_ALL_OUTPUTS(layer) \
do \
{ \
nvinfer1::ILayer* layer_ptr = layer; \
ASSERT(layer_ptr && "The input layer is null.", ErrorCode::kUNSUPPORTED_NODE); \
std::vector<TensorOrWeights> outputs; \
for (int i = 0; i < layer_ptr->getNbOutputs(); ++i) \
outputs.push_back(layer_ptr->getOutput(i)); \
return {outputs}; \
} while (0)
void assertIsWeights(TensorOrWeights const& input, std::string const& specificMsg)
{
if (!input.is_weights())
{
std::ostringstream msg;
msg << specificMsg;
msg << " Try applying constant folding on the model using Polygraphy: https://github.com/NVIDIA/TensorRT/tree/master/tools/Polygraphy/examples/cli/surgeon/02_folding_constants";
throw std::runtime_error(msg.str());
}
}
bool registerBuiltinOpImporter(std::string op, NodeImporter const& importer)
{
bool inserted = getBuiltinOpImporterMap().insert({op, importer}).second;
assert(inserted);
return inserted;
}
DEFINE_BUILTIN_OP_IMPORTER(Abs)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kABS);
}
DEFINE_BUILTIN_OP_IMPORTER(Acos)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kACOS);
}
DEFINE_BUILTIN_OP_IMPORTER(Acosh)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kACOSH);
}
DEFINE_BUILTIN_OP_IMPORTER(And)
{
return elementwiseHelper(ctx, node, inputs, nvinfer1::ElementWiseOperation::kAND);
}
DEFINE_BUILTIN_OP_IMPORTER(Asin)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kASIN);
}
DEFINE_BUILTIN_OP_IMPORTER(Asinh)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kASINH);
}
DEFINE_BUILTIN_OP_IMPORTER(Atan)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kATAN);
}
DEFINE_BUILTIN_OP_IMPORTER(Atanh)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kATANH);
}
DEFINE_BUILTIN_OP_IMPORTER(Add)
{
return elementwiseHelper(ctx, node, inputs, nvinfer1::ElementWiseOperation::kSUM);
}
DEFINE_BUILTIN_OP_IMPORTER(ArgMax)
{
return argMinMaxHelper(ctx, node, inputs, nvinfer1::TopKOperation::kMAX);
}
DEFINE_BUILTIN_OP_IMPORTER(ArgMin)
{
return argMinMaxHelper(ctx, node, inputs, nvinfer1::TopKOperation::kMIN);
}
DEFINE_BUILTIN_OP_IMPORTER(AveragePool)
{
return poolingHelper(ctx, node, inputs, nvinfer1::PoolingType::kAVERAGE);
}
NodeImportResult batchnormFallback(
IImporterContext* ctx, ::ONNX_NAMESPACE::NodeProto const& node, std::vector<TensorOrWeights>& inputs)
{
using eOp = nvinfer1::ElementWiseOperation;
using uOp = nvinfer1::UnaryOperation;
nvinfer1::ITensor& input = convertToTensor(inputs.at(0), ctx);
int32_t const rank = input.getDimensions().nbDims;
nvinfer1::ITensor* scale = &convertToTensor(inputs.at(1), ctx);
nvinfer1::ITensor* bias = &convertToTensor(inputs.at(2), ctx);
nvinfer1::ITensor* mean = &convertToTensor(inputs.at(3), ctx);
nvinfer1::ITensor* variance = &convertToTensor(inputs.at(4), ctx);
// Reshape batchnorm weights from [C] to [N, C, ...]
bool const needsExpandDims = rank > 1;
if (needsExpandDims)
{
std::vector<int32_t> axes(rank - 1);
axes[0] = 0;
std::iota(axes.begin() + 1, axes.end(), 2);
scale = unsqueezeTensor(ctx, node, *scale, axes);
bias = unsqueezeTensor(ctx, node, *bias, axes);
mean = unsqueezeTensor(ctx, node, *mean, axes);
variance = unsqueezeTensor(ctx, node, *variance, axes);
}
OnnxAttrs attrs(node, ctx);
float eps = attrs.get<float>("epsilon", 1e-5f);
nvinfer1::Dims scalarShape{rank};
std::fill(scalarShape.d, scalarShape.d + scalarShape.nbDims, 1);
nvinfer1::ITensor* epsilon
= addConstantScalar(ctx, eps, ::ONNX_NAMESPACE::TensorProto::FLOAT, scalarShape)->getOutput(0);
// batchnorm = scale * (input - mean) / sqrt(variance + epsilon) + bias
// The WAR is split the single c++ code line into 3 to avoid the sequence swap by compiler.
nvinfer1::ITensor* divisor
= ctx->network()
->addUnary(*ctx->network()->addElementWise(*variance, *epsilon, eOp::kSUM)->getOutput(0), uOp::kSQRT)
->getOutput(0);
nvinfer1::ITensor* dividend = ctx->network()->addElementWise(input, *mean, eOp::kSUB)->getOutput(0);
nvinfer1::IElementWiseLayer* layer = ctx->network()->addElementWise(
*ctx->network()
->addElementWise(
*scale, *ctx->network()->addElementWise(*dividend, *divisor, eOp::kDIV)->getOutput(0), eOp::kPROD)
->getOutput(0),
*bias, eOp::kSUM);
ctx->registerLayer(layer, getNodeName(node));
RETURN_FIRST_OUTPUT(layer);
}
DEFINE_BUILTIN_OP_IMPORTER(BatchNormalization)
{
ASSERT(
(inputs.at(1).shape().nbDims == 1) && "The shape of the scale input must be (C, )", ErrorCode::kINVALID_NODE);
ASSERT((inputs.at(2).shape().nbDims == 1) && "The shape of the bias input must be (C, )", ErrorCode::kINVALID_NODE);
ASSERT((inputs.at(3).shape().nbDims == 1) && "The shape of the mean input must be (C, )", ErrorCode::kINVALID_NODE);
ASSERT((inputs.at(4).shape().nbDims == 1) && "The shape of the var input must be (C, )", ErrorCode::kINVALID_NODE);
bool const allInputsWeights = inputs.at(1).is_weights() && inputs.at(2).is_weights() && inputs.at(3).is_weights()
&& inputs.at(4).is_weights();
if (!allInputsWeights)
{
return batchnormFallback(ctx, node, inputs);
}
auto const scale = inputs.at(1).weights();
auto const bias = inputs.at(2).weights();
auto const mean = inputs.at(3).weights();
auto const variance = inputs.at(4).weights();
// get the values of constant inputs and cast them to float32
auto const getValuesFP32 = [&](ShapedWeights const& w) -> float const* {
return (w.type == ::ONNX_NAMESPACE::TensorProto::FLOAT) ? static_cast<float*>(w.values)
: convertFP16Data(w.values, w.shape, ctx);
};
float const* scaleValues = getValuesFP32(scale);
float const* biasValues = getValuesFP32(bias);
float const* meanValues = getValuesFP32(mean);
float const* varianceValues = getValuesFP32(variance);
nvinfer1::ITensor* tensorPtr = &convertToTensor(inputs.at(0), ctx);
OnnxAttrs attrs(node, ctx);
float eps = attrs.get<float>("epsilon", 1e-5f);
// Fold the weights together into a single bias and scale
int32_t const nbChannels = scale.shape.d[0];
auto combinedScale = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, scale.shape);
auto combinedBias = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, bias.shape);
for (int32_t i = 0; i < nbChannels; ++i)
{
combinedScale.at<float>(i) = scaleValues[i] / sqrtf(varianceValues[i] + eps);
combinedBias.at<float>(i) = biasValues[i] - meanValues[i] * combinedScale.at<float>(i);
}
return scaleHelper(ctx, node, *tensorPtr, nvinfer1::ScaleMode::kCHANNEL, combinedBias, combinedScale,
ShapedWeights::empty(::ONNX_NAMESPACE::TensorProto::FLOAT), combinedBias.getName(), combinedScale.getName());
}
DEFINE_BUILTIN_OP_IMPORTER(Cast)
{
// Get input node.
nvinfer1::ITensor& tensor = convertToTensor(inputs.at(0), ctx);
OnnxAttrs attrs(node, ctx);
// Get data type to cast to.
DataType dtype = tensor.getType();
auto onnxType = attrs.get<int32_t>("to");
DataType newType{DataType::kFLOAT};
ASSERT(
convertDtype(onnxType, &newType) && "Unsupported data type for the Cast operator!", ErrorCode::kINVALID_NODE);
LOG_VERBOSE("Casting to type: " << newType);
// UINT8 type casting is only supported from FP types.
if (dtype == DataType::kUINT8)
{
ASSERT(newType == DataType::kFLOAT || newType == DataType::kHALF, ErrorCode::kUNSUPPORTED_NODE);
}
if (newType == DataType::kUINT8)
{
ASSERT(dtype == DataType::kFLOAT || dtype == DataType::kHALF, ErrorCode::kUNSUPPORTED_NODE);
}
// Add the layer.
nvinfer1::IIdentityLayer* layer = ctx->network()->addIdentity(tensor);
layer->setOutputType(0, newType);
ctx->registerLayer(layer, getNodeName(node));
RETURN_FIRST_OUTPUT(layer);
}
DEFINE_BUILTIN_OP_IMPORTER(Ceil)
{
return unaryHelper(ctx, node, inputs.at(0), nvinfer1::UnaryOperation::kCEIL);
}
DEFINE_BUILTIN_OP_IMPORTER(Celu)
{
using eOp = nvinfer1::ElementWiseOperation;
using uOp = nvinfer1::UnaryOperation;
using eOpInstuctor = std::tuple<int, int, const nvinfer1::ElementWiseOperation>;
ASSERT( (!inputs.empty()) && "Inputs vector is empty.", ErrorCode::kINVALID_NODE);
OnnxAttrs attrs(node, ctx);
TensorOrWeights input = inputs.at(0);
float alpha = attrs.get<float>("alpha", 1.0);
TensorOrWeights weightsOfZero = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, {0,{}});
ShapedWeights weightsOfOnes = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, {0,{}});
std::vector<float> ones{1};
std::memcpy(weightsOfOnes.values, ones.data(), weightsOfOnes.count() * sizeof(float));
ShapedWeights weightsOfAlpha = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, {0,{}});
std::vector<float> alphas{alpha};
std::memcpy(weightsOfAlpha.values, alphas.data(), weightsOfAlpha.count() * sizeof(float));
// Variable name -> index in inputTensors
// x -> 0
// 0 -> 1
// 1 -> 2
// alpha -> 3
std::vector<TensorOrWeights> newInputs{input, weightsOfZero, weightsOfOnes, weightsOfAlpha};
std::vector<nvinfer1::ITensor*> inputTensors;
int32_t maxNbDims = -1;
for (auto i : newInputs)
{
maxNbDims = std::max(maxNbDims, i.shape().nbDims);
}
for (auto i : newInputs)
{
auto* tensor_ptr = &convertToTensor(i, ctx);
// Broadcast all input tensors to size of maxNbDims
broadcastTensor(ctx, tensor_ptr, maxNbDims);
ASSERT(tensor_ptr->getDimensions().nbDims == maxNbDims && "Failed to broadcast tensors elementwise!",
ErrorCode::kUNSUPPORTED_NODE);
inputTensors.push_back(tensor_ptr);
}
// Calculate (x/alpha)
std::vector<TensorOrWeights> tempInputs{newInputs[0], newInputs[3]};
ASSERT(elementwiseCheck(tempInputs, eOp::kDIV) && "Elementwise layer does not support the given inputs and operator.", ErrorCode::kUNSUPPORTED_NODE);
nvinfer1::ITensor* combined = inputTensors.at(0);
auto* divLayer = ctx->network()->addElementWise(*combined, *inputTensors.at(3), eOp::kDIV);
ctx->registerLayer(divLayer, getNodeName(node));
ASSERT(divLayer && "Failed to register layer.", ErrorCode::kUNSUPPORTED_NODE);
combined = divLayer->getOutput(0);
// Calculate exp(x/alpha) -> 4
nvinfer1::IUnaryLayer* uLayer = ctx->network()->addUnary(*combined, uOp::kEXP);
ctx->registerLayer(uLayer, getNodeName(node));
combined = uLayer->getOutput(0);
inputTensors.push_back(combined);
std::vector<eOpInstuctor> operations{
// max(0,x) -> 5
eOpInstuctor(0, 1, eOp::kMAX),
// (exp(x/alpha)-1)) -> 6
eOpInstuctor(4, 2, eOp::kSUB),
// alpha*(exp(x/alpha)-1) -> 7
eOpInstuctor(3, 6, eOp::kPROD),
// min(0,alpha*(exp(x/alpha)-1)) -> 8
eOpInstuctor(1, 7, eOp::kMIN),
// max(0,x) + min(0,alpha*(exp(x/alpha)-1)) -> 9
eOpInstuctor(5, 8, eOp::kSUM),
};
for (auto it : operations)
{
nvinfer1::ITensor* firstTensor = inputTensors.at(std::get<0>(it));
nvinfer1::ITensor* secondTensor = inputTensors.at(std::get<1>(it));
eOp const op = std::get<2>(it);
tempInputs = {firstTensor, secondTensor};
ASSERT(
(elementwiseCheck(tempInputs, op)) && "Elementwise layer does not support the given inputs and operator.",
ErrorCode::kUNSUPPORTED_NODE);
ASSERT((firstTensor->getDimensions().nbDims == secondTensor->getDimensions().nbDims)
&& "The number of dimensions should remain the same adding inputs.",
ErrorCode::kUNSUPPORTED_NODE);
auto* layer = ctx->network()->addElementWise(*firstTensor, *secondTensor, op);
ctx->registerLayer(layer, getNodeName(node));
ASSERT(layer && "Failed to register layer.", ErrorCode::kUNSUPPORTED_NODE);
inputTensors.push_back(layer->getOutput(0));
}
return {{inputTensors.back()}};
}
// Helper function to perform clip through elementwise operations
template <typename ScalarType>
NodeImportResult elementwiseClipHelper(IImporterContext* ctx, ::ONNX_NAMESPACE::NodeProto const& node,
std::vector<TensorOrWeights>& inputs, size_t numInputs, int32_t onnxType)
{
OnnxAttrs attrs(node, ctx);
auto* input = &convertToTensor(inputs.at(0), ctx);
nvinfer1::ITensor* alphaT{nullptr};
nvinfer1::ITensor* betaT{nullptr};
ScalarType alpha = std::numeric_limits<ScalarType>::lowest();
ScalarType beta = std::numeric_limits<ScalarType>::max();
if (ctx->getOpsetVersion() >= 11)
{
if (numInputs == 1)
{
alphaT = addConstantScalar(ctx, alpha, onnxType)->getOutput(0);
betaT = addConstantScalar(ctx, beta, onnxType)->getOutput(0);
}
else if (numInputs == 2)
{
alphaT = &convertToTensor(inputs.at(1), ctx);
betaT = addConstantScalar(ctx, beta, onnxType)->getOutput(0);
}
else if (numInputs == 3)
{
// "min" can be optional if "max" is specified. Check for this case here
if (!inputs.at(1).isNullTensor())
{
alphaT = &convertToTensor(inputs.at(1), ctx);
}
else
{
alphaT = addConstantScalar(ctx, alpha, onnxType)->getOutput(0);
}
if (!inputs.at(2).isNullTensor())
{
betaT = &convertToTensor(inputs.at(2), ctx);
}
else
{
betaT = addConstantScalar(ctx, beta, onnxType)->getOutput(0);
}
}
}
else
{
alpha = static_cast<ScalarType>(attrs.get("min", alpha));
alphaT = addConstantScalar(ctx, alpha, onnxType)->getOutput(0);
beta = static_cast<ScalarType>(attrs.get("max", beta));
betaT = addConstantScalar(ctx, beta, onnxType)->getOutput(0);
}
// Now that we have alphaT and betaT, do the elementwise calculation
using eOp = nvinfer1::ElementWiseOperation;
CHECK(broadcastTensors(ctx, input, alphaT));
CHECK(broadcastTensors(ctx, input, betaT));
auto lowerClip = ctx->network()->addElementWise(*input, *alphaT, eOp::kMAX)->getOutput(0);
auto upperClip = ctx->network()->addElementWise(*lowerClip, *betaT, eOp::kMIN)->getOutput(0);
return {{upperClip}};
}
DEFINE_BUILTIN_OP_IMPORTER(Clip)
{
CHECK(notInvalidType(inputs.at(0), {"UINT8"}));
// For INT32 and multi-input clips, use elementwise operators instead.
size_t numInputs = inputs.size();
bool elementwiseClip = inputs.at(0).isInt32();
for (size_t i = 1; i < numInputs; i++)
{
elementwiseClip |= inputs.at(i).is_tensor();
}
if (elementwiseClip)
{
auto type = convertToTensor(inputs.at(0), ctx).getType();
ASSERT((type == DataType::kFLOAT || type == DataType::kHALF || type == DataType::kINT32)
&& "This version of TensorRT only supports FLOAT or INT32 inputs for Clip!",
ErrorCode::kUNSUPPORTED_NODE);
if (type == DataType::kFLOAT || type == DataType::kHALF)
{
return elementwiseClipHelper<float>(ctx, node, inputs, numInputs, ::ONNX_NAMESPACE::TensorProto::FLOAT);
}
else
{
return elementwiseClipHelper<int32_t>(ctx, node, inputs, numInputs, ::ONNX_NAMESPACE::TensorProto::INT32);
}
}
// Activation path only supports float/half initializers
OnnxAttrs attrs(node, ctx);
// beta is the upper bound
float alpha = std::numeric_limits<float>::lowest();
float beta = std::numeric_limits<float>::max();
bool fp16 = inputs.at(0).isFp16();
if (ctx->getOpsetVersion() >= 11)
{
// Handle "min" node input.
if (numInputs == 2)
{
ASSERT(inputs.at(1).is_weights() && "Clip min value must be an initializer!", ErrorCode::kUNSUPPORTED_NODE);
auto min = inputs.at(1).weights();
alpha = getSingleValueAsFloat(min.values, /*isFp16*/ fp16);
}
// Handle both "min" and "max" node inputs
else if (numInputs == 3)
{
// "min" can be optional if "max" is specified. Check for this case here
if (!inputs.at(1).isNullTensor())
{
ASSERT(inputs.at(1).is_weights() && "Clip min value must be an initializer!",
ErrorCode::kUNSUPPORTED_NODE);
auto min = inputs.at(1).weights();
alpha = getSingleValueAsFloat(min.values, /*isFp16*/ fp16);
}
if (!inputs.at(2).isNullTensor())
{
ASSERT(inputs.at(2).is_weights() && "Clip max value must be an initializer!",
ErrorCode::kUNSUPPORTED_NODE);
auto max = inputs.at(2).weights();
beta = getSingleValueAsFloat(max.values, /*isFp16*/ fp16);
}
}
}
else
{
alpha = attrs.get("min", std::numeric_limits<float>::lowest());
beta = attrs.get("max", std::numeric_limits<float>::max());
}
nvinfer1::ITensor* clipOut
= &activationHelper(ctx, node, inputs, nvinfer1::ActivationType::kCLIP, &alpha, &beta).value().at(0).tensor();
return {{clipOut}};
}
DEFINE_BUILTIN_OP_IMPORTER(Concat)
{
CHECK(notInvalidType(inputs.at(0), {"UINT8"}));
std::vector<nvinfer1::ITensor*> tensors;
for (auto& input : inputs)
{
auto* tensorPtr = &convertToTensor(input, ctx);
tensors.push_back(tensorPtr);
}
OnnxAttrs attrs(node, ctx);
int32_t axis = attrs.get<int32_t>("axis");
int32_t nbDims = inputs.at(0).shape().nbDims;
CHECK(convertAxis(axis, nbDims));
auto* layer = ctx->network()->addConcatenation(tensors.data(), tensors.size());
ctx->registerLayer(layer, getNodeName(node));
ASSERT(layer && "Failed to register layer.", ErrorCode::kUNSUPPORTED_NODE);
layer->setAxis(axis);
RETURN_FIRST_OUTPUT(layer);
}
DEFINE_BUILTIN_OP_IMPORTER(Constant)
{
OnnxAttrs attrs(node, ctx);
// Having the trt_outputs_range_min attributes means it's from
// serialized iNetworkDefinition.
if (!attrs.get<std::vector<float>>("trt_outputs_range_min", {}).empty())
{
// just create a constant layer here for 1-1 mapping during network deserialization
auto weights = attrs.get<ShapedWeights>("value");
auto* layer = ctx->network()->addConstant(weights.shape, weights);
ctx->network()->setWeightsName(weights, weights.getName());
RETURN_FIRST_OUTPUT(layer);
}
ASSERT((!attrs.count("sparse_value")) && (!attrs.count("value_string")) && (!attrs.count("value_strings"))
&& "This version of TensorRT does not support the sparse_value, value_string and value_strings attributes.", ErrorCode::kUNSUPPORTED_NODE);
if (ctx->getOpsetVersion() >=12)
{
if (attrs.count("value_float"))
{
ShapedWeights convertedWeights = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, {0,{}});
float value = attrs.get<float>("value_float");
std::memcpy(convertedWeights.values, &value, convertedWeights.count() * sizeof(float));
return {{convertedWeights}};
}
if (attrs.count("value_floats"))
{
std::vector<float> values = attrs.get<std::vector<float>>("value_floats");
int32_t valueSize = values.size();
ShapedWeights convertedWeights
= ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::FLOAT, {1, {valueSize}});
std::memcpy(convertedWeights.values, values.data(), convertedWeights.count() * sizeof(float));
return {{convertedWeights}};
}
if (attrs.count("value_int"))
{
ShapedWeights convertedWeights = ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::INT32, {0,{}});
float value = attrs.get<float>("value_int");
std::memcpy(convertedWeights.values, &value, convertedWeights.count() * sizeof(int));
return {{convertedWeights}};
}
if (attrs.count("value_ints"))
{
std::vector<float> values = attrs.get<std::vector<float>>("value_ints");
int32_t valueSize = values.size();
ShapedWeights convertedWeights
= ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto::INT32, {1, {valueSize}});
std::memcpy(convertedWeights.values, values.data(), convertedWeights.count() * sizeof(float));
return {{convertedWeights}};
}
}
return {{attrs.get<ShapedWeights>("value")}};
}
DEFINE_BUILTIN_OP_IMPORTER(ConstantOfShape)
{
OnnxAttrs attrs(node, ctx);
nvinfer1::ITensor* shape = &convertToTensor(inputs.at(0), ctx);
ShapedWeights zeroWeights
= ctx->createTempWeights(::ONNX_NAMESPACE::TensorProto_DataType_FLOAT, nvinfer1::Dims{1, 1});
static_cast<float*>(zeroWeights.values)[0] = 0.f;
auto valueWeights = TensorOrWeights{attrs.get("value", zeroWeights)};
CHECK(notInvalidType(valueWeights, {"UINT8"}));
nvinfer1::ITensor* value = &convertToTensor(valueWeights, ctx);
return {{constantOfShape(ctx, node, value, shape)}};
}
DEFINE_BUILTIN_OP_IMPORTER(Conv)
{
if (inputs.at(1).is_tensor() || (inputs.size() > 2 && inputs.at(2).is_tensor()))
{
// Handle dynamic weights convolution
return convMultiInput(ctx, node, inputs);
}
nvinfer1::ITensor* tensorPtr = &convertToTensor(inputs.at(0), ctx);
auto kernelWeights = inputs.at(1).weights();
nvinfer1::Dims dims = tensorPtr->getDimensions();
LOG_VERBOSE("Convolution input dimensions: " << dims);
ASSERT(dims.nbDims >= 0 && "TensorRT could not compute output dimensions of Conv", ErrorCode::kUNSUPPORTED_NODE);
bool const needToExpandDims = (dims.nbDims == 3);
if (needToExpandDims)
{
// Expand spatial dims from 1D to 2D
std::vector<int> axes{3};
tensorPtr = unsqueezeTensor(ctx, node, *tensorPtr, axes);
ASSERT(tensorPtr && "Failed to unsqueeze tensor.", ErrorCode::kUNSUPPORTED_NODE);
dims = tensorPtr->getDimensions();
}
if (kernelWeights.shape.nbDims == 3)
{
kernelWeights.shape.nbDims = 4;
kernelWeights.shape.d[3] = 1;
}
int32_t const nbSpatialDims = dims.nbDims - 2;
// Check that the number of spatial dimensions and the kernel shape matches up.
ASSERT((nbSpatialDims == kernelWeights.shape.nbDims - 2)
&& "The number of spatial dimensions and the kernel shape doesn't match up for the Conv operator.",
ErrorCode::kUNSUPPORTED_NODE);
nvinfer1::Weights bias_weights;
if (inputs.size() == 3)
{
assertIsWeights(inputs.at(2), "The bias tensor is required to be an initializer for the Conv operator.");
auto shapedBiasWeights = inputs.at(2).weights();
// Unsqueeze scalar weights to 1D
if (shapedBiasWeights.shape.nbDims == 0)
{
shapedBiasWeights.shape = {1, {1}};
}
ASSERT( (shapedBiasWeights.shape.nbDims == 1) && "The bias tensor is required to be 1D.", ErrorCode::kINVALID_NODE);
ASSERT( (shapedBiasWeights.shape.d[0] == kernelWeights.shape.d[0]) && "The shape of the bias tensor misaligns with the weight tensor.", ErrorCode::kINVALID_NODE);
bias_weights = shapedBiasWeights;
}
else
{
bias_weights = ShapedWeights::empty(kernelWeights.type);
}
nvinfer1::Dims kernelSize;
kernelSize.nbDims = nbSpatialDims;
for (int32_t i = 1; i <= nbSpatialDims; ++i)
{
kernelSize.d[nbSpatialDims - i] = kernelWeights.shape.d[kernelWeights.shape.nbDims - i];
}
nvinfer1::Dims strides = makeDims(nbSpatialDims, 1);
nvinfer1::Dims begPadding = makeDims(nbSpatialDims, 0);
nvinfer1::Dims endPadding = makeDims(nbSpatialDims, 0);
nvinfer1::Dims dilations = makeDims(nbSpatialDims, 1);
nvinfer1::PaddingMode paddingMode;
bool exclude_padding;
getKernelParams(
ctx, node, &kernelSize, &strides, &begPadding, &endPadding, paddingMode, exclude_padding, &dilations);
for (int32_t i = 1; i <= nbSpatialDims; ++i)
{
ASSERT((kernelSize.d[nbSpatialDims - i] == kernelWeights.shape.d[kernelWeights.shape.nbDims - i])
&& "The size of spatial dimension and the size of kernel shape are not equal for the Conv operator.",
ErrorCode::kUNSUPPORTED_NODE);
}
int32_t nchan = dims.d[1];
int32_t noutput = kernelWeights.shape.d[0];
nvinfer1::IConvolutionLayer* layer
= ctx->network()->addConvolutionNd(*tensorPtr, noutput, kernelSize, kernelWeights, bias_weights);
ASSERT(layer && "Failed to add a convolution layer.", ErrorCode::kUNSUPPORTED_NODE);
layer->setStrideNd(strides);
layer->setPaddingMode(paddingMode);
layer->setPrePadding(begPadding);
layer->setPostPadding(endPadding);
layer->setDilationNd(dilations);
OnnxAttrs attrs(node, ctx);
int32_t ngroup = attrs.get("group", 1);
ASSERT((nchan == -1 || kernelWeights.shape.d[1] * ngroup == nchan)
&& "Kernel weight dimension failed to broadcast to input.",
ErrorCode::kINVALID_NODE);
layer->setNbGroups(ngroup);
// Register layer name as well as kernel weights and bias weights (if any)
ctx->registerLayer(layer, getNodeName(node));
ctx->network()->setWeightsName(kernelWeights, inputs.at(1).weights().getName());
if (inputs.size() == 3)
{
ctx->network()->setWeightsName(bias_weights, inputs.at(2).weights().getName());
}
tensorPtr = layer->getOutput(0);
dims = tensorPtr->getDimensions();
if (needToExpandDims)
{
// Un-expand spatial dims back to 1D
std::vector<int> axes{3};
tensorPtr = squeezeTensor(ctx, node, *tensorPtr, axes);
ASSERT(tensorPtr && "Failed to unsqueeze tensor.", ErrorCode::kUNSUPPORTED_NODE);
}
LOG_VERBOSE("Using kernel: " << kernelSize << ", strides: " << strides << ", prepadding: " << begPadding
<< ", postpadding: " << endPadding << ", dilations: " << dilations << ", numOutputs: " << noutput);
LOG_VERBOSE("Convolution output dimensions: " << dims);
return {{tensorPtr}};
}
// TRT only supports 2D or 3D deconvolutions (Layout: [N,C,D1,D2,(D3)])
// Inputs should be of dimension 4 or 5.
// When input.nbDims = 3, we expand it to 4D
DEFINE_BUILTIN_OP_IMPORTER(ConvTranspose)
{
// Expand spatial dims from 1D to 2D, return true if reshaped activation
auto const NCWtoNCHW = [&ctx, &node](nvinfer1::ITensor*& tensor, nvinfer1::Dims& tensorShape) {
if (tensor && tensor->getDimensions().nbDims == 3)
{
std::vector<int32_t> const axes{3};
tensor = unsqueezeTensor(ctx, node, *tensor, axes);
tensorShape = tensor->getDimensions();
return true;
}
// for initializer, just change the shape by appending 1
if (tensorShape.nbDims == 3)
{
tensorShape.nbDims = 4;
tensorShape.d[3] = 1;
}
return false;
};
ASSERT(inputs.size() >= 2 && "deconvolution require at least 2 inputs.", ErrorCode::kUNSUPPORTED_NODE);
nvinfer1::ITensor* tensorPtr = &convertToTensor(inputs.at(0), ctx);
nvinfer1::ITensor* kernelTensorPtr = inputs.at(1).is_tensor() ? &convertToTensor(inputs.at(1), ctx) : nullptr;
nvinfer1::ITensor* biasTensorPtr
= inputs.size() > 2 && inputs.at(2).is_tensor() ? &convertToTensor(inputs.at(2), ctx) : nullptr;
nvinfer1::Dims dims = tensorPtr->getDimensions();
// Deconvolution input must be at least 3D and at most 5D.
ASSERT(dims.nbDims >= 3 && dims.nbDims <= 5 && "TensorRT only supports 1D, 2D or 3D deconvolutions!",
ErrorCode::kUNSUPPORTED_NODE);
// Kernel weights have layout [C, M/group, k1, k2, (k3)]
auto kernelShape = inputs.at(1).shape();
bool needReshapeBack = NCWtoNCHW(tensorPtr, dims);
NCWtoNCHW(kernelTensorPtr, kernelShape);
int32_t const nbSpatialDims = dims.nbDims - 2;
// Check that the number of spatial dimensions and the kernel shape matches up.
ASSERT((nbSpatialDims == kernelShape.nbDims - 2)
&& "The number of spatial dimensions and the kernel shape doesn't match up",
ErrorCode::kUNSUPPORTED_NODE);
// Get all attributes
OnnxAttrs attrs(node, ctx);
nvinfer1::Dims outputShape;
nvinfer1::Dims outputPadding = makeDims(nbSpatialDims, 0);
nvinfer1::Dims kernelSize;
nvinfer1::Dims strides = makeDims(nbSpatialDims, 1);
nvinfer1::Dims begPadding = makeDims(nbSpatialDims, 0);
nvinfer1::Dims endPadding = makeDims(nbSpatialDims, 0);
nvinfer1::Dims dilations = makeDims(nbSpatialDims, 1);
nvinfer1::PaddingMode paddingMode;
bool exclude_padding = false;
int32_t ngroup = attrs.get("group", 1);
int32_t noutput = kernelShape.d[1] * ngroup; // Note: Weights order is CKRS
// Get static bias weights
nvinfer1::Weights staticBiasWeights;
if (inputs.size() > 2 && biasTensorPtr == nullptr)
{
auto shapedBiasWeights = inputs.at(2).weights();
// ONNX requires shapedBiasWeights to be 1D
ASSERT(
shapedBiasWeights.shape.nbDims == 1 && "The bias tensor is required to be 1D.", ErrorCode::kINVALID_NODE);
ASSERT((shapedBiasWeights.shape.d[0] == noutput)
&& "The shape of the bias tensor does not align with the shape of the output.",
ErrorCode::kINVALID_NODE);
staticBiasWeights = shapedBiasWeights;
}
else
{
staticBiasWeights = ShapedWeights::empty(::ONNX_NAMESPACE::TensorProto::FLOAT);
}
// Kernel shape either comes from the attributes or extracted from the kernel weights shape
kernelSize.nbDims = nbSpatialDims;
for (int32_t i = 1; i <= nbSpatialDims; ++i)
{
kernelSize.d[nbSpatialDims - i] = kernelShape.d[kernelShape.nbDims - i];
}
getKernelParams(ctx, node, &kernelSize, &strides, &begPadding, &endPadding, paddingMode, exclude_padding,
&dilations, &outputPadding);
for (int32_t i = 1; i <= nbSpatialDims; ++i)
{
ASSERT((kernelSize.d[nbSpatialDims - i] == kernelShape.d[kernelShape.nbDims - i])
&& "Attribute kernel_shape misaligns with the dimensions of the weight tensor.",
ErrorCode::kUNSUPPORTED_NODE);
}
// Set padding. ONNX ConvTranspose supports many different padding modes. Order of priority for padding:
// 1. Output shape is specified - calculate expected pre and post padding.
// 2. AUTO_PAD != NOTSET: ignore all other padding values and set padding mode with layer->setPaddingMode.
// Pad the resulting output vector with values from output_padding
// 3. Use specified "pads" values from the node. Pad the resulting output vector with values from output_padding
auto autoPadMode = attrs.get("auto_pad", std::string("NOTSET"));
if (attrs.count("output_shape") && autoPadMode == std::string("NOTSET"))
{
outputShape = attrs.get<nvinfer1::Dims>("output_shape");
// This function takes references to begPadding, endPadding and outputPadding and will update them with correct values
generatePadding(dims, outputShape, kernelSize, strides, dilations, nbSpatialDims, begPadding, endPadding,
outputPadding, paddingMode);
// NOTE: it is possible for generatePadding to produce negative values for pre and post padding, which usually
// happens when output_shape is provided but output_padding is not. Any negative values generated for
// post-padding can be translated into outputPadding to pad the output tensor post deconvolution. Any negative
// values for pre-padding are unsupported.
for (int32_t i = 0; i < nbSpatialDims; i++)
{
ASSERT(
begPadding.d[i] >= 0 && "TensorRT does not support negative pre-padding in the ConvTranspose operator!",
ErrorCode::kUNSUPPORTED_NODE);
// Update outputPadding with any negative values in endPadding, and set the corresponding value to 0.
if (endPadding.d[i] < 0)
{
outputPadding.d[i] = endPadding.d[i] * -1;
endPadding.d[i] = 0;
}
}
}
// When there is output_padding, if postPadding is larger than outputPadding, just adjust postPadding
// Or reduce outputPadding as minimum as possible.
bool hasOutputPadding = false;
if (outputPadding != makeDims(nbSpatialDims, 0) && autoPadMode == std::string("NOTSET"))
{
for (int32_t i = 0; i < nbSpatialDims; ++i)
{
if (endPadding.d[i] - outputPadding.d[i] >= 0)
{
endPadding.d[i] -= outputPadding.d[i];
outputPadding.d[i] = 0;
}
else
{
// Reduce outputPadding as possible.
outputPadding.d[i] -= endPadding.d[i];
endPadding.d[i] = 0;
hasOutputPadding = true;
}
}
}
auto const emptyBiasWeights = ShapedWeights::empty(::ONNX_NAMESPACE::TensorProto::FLOAT);
auto const kernelWeights
= kernelTensorPtr ? nvinfer1::Weights{DataType::kFLOAT, nullptr, 0} : inputs.at(1).weights();
const auto biasWeights
= biasTensorPtr ? nvinfer1::Weights{DataType::kFLOAT, nullptr, 0} : staticBiasWeights;
// Create a deconvolution layer and set known attributes - strides,ngroups, and dilations
// If there is still output padding, remove the bias weights. Bias will be added below.
auto* layer = ctx->network()->addDeconvolutionNd(
*tensorPtr, noutput, kernelSize, kernelWeights, hasOutputPadding ? emptyBiasWeights : biasWeights);
layer->setStrideNd(strides);
layer->setNbGroups(ngroup);
layer->setDilationNd(dilations);
if (kernelTensorPtr)
{
layer->setInput(1, *kernelTensorPtr);
}
else
{
ctx->network()->setWeightsName(kernelWeights, inputs.at(1).weights().getName());
}
if (biasTensorPtr)
{
layer->setInput(2, *biasTensorPtr);
}
layer->setPaddingMode(paddingMode);
layer->setPrePadding(begPadding);
layer->setPostPadding(endPadding);
LOG_VERBOSE("Running deconvolution with: "
<< "\n"
<< "Padding mode: " << autoPadMode << "\n"
<< "Pre-padding: " << begPadding << "\n"
<< "Post-padding: " << endPadding);
// Register layer, along with refittable kernel weights and bias weights (if any)
ctx->registerLayer(layer, getNodeName(node));
tensorPtr = layer->getOutput(0);
dims = tensorPtr->getDimensions();
// There is still output padding. Add a padding layer to handle it.
if (hasOutputPadding)
{
LOG_VERBOSE("Padding output deconvolution tensor with: " << outputPadding);
// Add padding layer
nvinfer1::ITensor* start{};
nvinfer1::ITensor* totalPadding{};
std::vector<int32_t> combinePadding{};
for (int32_t i = 0; i < outputPadding.nbDims; ++i)
{
combinePadding.insert(combinePadding.begin(), 0);
combinePadding.push_back(outputPadding.d[i]);
}
ASSERT(
convertOnnxPadding(ctx, dims.nbDims, combinePadding, start, totalPadding) && "Failed to convert padding!",
ErrorCode::kUNSUPPORTED_NODE);
auto const size
= ctx->network()
->addElementWise(shapeOf(*tensorPtr).tensor(ctx), *totalPadding, nvinfer1::ElementWiseOperation::kSUM)
->getOutput(0);
auto const stride = makeDims(dims.nbDims, 1);
auto const& dummy = stride;
auto* sliceLayer = ctx->network()->addSlice(*tensorPtr, dummy, dummy, stride);
ASSERT(sliceLayer && "Could not create padding layer", ErrorCode::kUNSUPPORTED_NODE);
sliceLayer->setInput(1, *start);
sliceLayer->setInput(2, *size);
sliceLayer->setMode(nvinfer1::SliceMode::kFILL);
tensorPtr = sliceLayer->getOutput(0);
// This bias is not handled by deconv. Use an elementwise to handle it.
if (biasWeights.count != 0)
{
// Set C dimension to weights count and set other dimensions to 1 to enable broadcast
auto constantDims = makeDims(dims.nbDims, 1);