Added to the builder rules also ".sv" source extensions, for system v…

…erilog.
FPGAwars · Jan 2, 2025 · aef87d1 · aef87d1
1 parent 8c9c1ea
commit aef87d1
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Showing 6 changed files with 14 additions and 32 deletions.
diff --git a/apio/scons/plugin_base.py b/apio/scons/plugin_base.py
@@ -102,7 +102,7 @@ def yosys_dot_builder(self) -> BuilderBase:
                 "" if args.VERBOSE_ALL else "-q",
             ),
             suffix=".dot",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 

diff --git a/apio/scons/plugin_ecp5.py b/apio/scons/plugin_ecp5.py
@@ -66,7 +66,7 @@ def synth_builder(self) -> BuilderBase:
                 "" if args.VERBOSE_ALL or args.VERBOSE_YOSYS else "-q",
             ),
             suffix=".json",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -155,7 +155,7 @@ def action_generator(source, target, env, for_signature):
             # -- Dynamic action string generator.
             generator=action_generator,
             suffix=".out",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -191,6 +191,6 @@ def lint_builder(self) -> BuilderBase:
                 top_module=args.TOP_MODULE,
                 lib_dirs=[self.yosys_lib_dir],
             ),
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
diff --git a/apio/scons/plugin_gowin.py b/apio/scons/plugin_gowin.py
@@ -62,7 +62,7 @@ def synth_builder(self) -> BuilderBase:
                 "" if args.VERBOSE_ALL or args.VERBOSE_YOSYS else "-q",
             ),
             suffix=".json",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -145,7 +145,7 @@ def action_generator(source, target, env, for_signature):
             # -- Dynamic action string generator.
             generator=action_generator,
             suffix=".out",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -177,6 +177,6 @@ def lint_builder(self) -> BuilderBase:
                 top_module=args.TOP_MODULE,
                 lib_dirs=[self.yosys_lib_dir],
             ),
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
diff --git a/apio/scons/plugin_ice40.py b/apio/scons/plugin_ice40.py
@@ -62,7 +62,7 @@ def synth_builder(self) -> BuilderBase:
                 "" if args.VERBOSE_ALL or args.VERBOSE_YOSYS else "-q",
             ),
             suffix=".json",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -142,7 +142,7 @@ def action_generator(source, target, env, for_signature):
             # -- Dynamic action string generator.
             generator=action_generator,
             suffix=".out",
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
 
@@ -175,6 +175,6 @@ def lint_builder(self) -> BuilderBase:
                 extra_params=["-DNO_ICE40_DEFAULT_ASSIGNMENTS"],
                 lib_files=[self.yosys_lib_file],
             ),
-            src_suffix=".v",
+            src_suffix=[".v", ".sv"],
             source_scanner=self.verilog_src_scanner,
         )
diff --git a/apio/scons/plugin_util.py b/apio/scons/plugin_util.py
@@ -365,14 +365,11 @@ def get_tests_configs(
     return configs
 
 
-def is_verilog_src(file_name: str, *, include_sv: bool = True) -> bool:
+def is_verilog_src(file_name: str) -> bool:
     """Given a file name, determine by its extension if it's a verilog
-    source file (testbenches included).  If include_sv is True, include
-    also system verilog files."""
+    source file (testbenches included)."""
     _, ext = os.path.splitext(file_name)
-    if include_sv:
-        return ext in [".v", ".sv"]
-    return ext in [".v"]
+    return ext in [".v", ".sv"]
 
 
 def has_testbench_name(file_name: str) -> bool:

diff --git a/test/scons/test_plugin_util.py b/test/scons/test_plugin_util.py
@@ -133,7 +133,7 @@ def test_verilog_src_scanner(apio_runner: ApioRunner):
 def test_is_verilog_src():
     """Tests the is_verilog_src() function."""
 
-    # -- Verilog and system-verilog source names, system-verilog included.
+    # -- Verilog and system-verilog source names,
     assert is_verilog_src("aaa.v")
     assert is_verilog_src("bbb/aaa.v")
     assert is_verilog_src("bbb\\aaa.v")
@@ -143,26 +143,11 @@ def test_is_verilog_src():
     assert is_verilog_src("bbb\\aaa.sv")
     assert is_verilog_src("aaa_tb.sv")
 
-    # -- Verilog and system-verilog source names, system-verilog excluded.
-    assert is_verilog_src("aaa.v", include_sv=False)
-    assert is_verilog_src("bbb/aaa.v", include_sv=False)
-    assert is_verilog_src("bbb\\aaa.v", include_sv=False)
-    assert is_verilog_src("aaatb.v", include_sv=False)
-    assert is_verilog_src("aaa_tb.v", include_sv=False)
-    assert not is_verilog_src("aaa.sv", include_sv=False)
-    assert not is_verilog_src("bbb\\aaa.sv", include_sv=False)
-    assert not is_verilog_src("aaa_tb.sv", include_sv=False)
-
     # -- Non verilog source names, system-verilog included.
     assert not is_verilog_src("aaatb.vv")
     assert not is_verilog_src("aaatb.V")
     assert not is_verilog_src("aaa_tb.vh")
 
-    # -- Non verilog source names, system-verilog excluded.
-    assert not is_verilog_src("aaatb.vv", include_sv=False)
-    assert not is_verilog_src("aaatb.V", include_sv=False)
-    assert not is_verilog_src("aaa_tb.vh", include_sv=False)
-
 
 def test_has_testbench_name():
     """Tests the test_is_testbench() function."""