va: jz4780: Add Ingenic video acceleration support

Change-Id: I00443f0a0f4d616623942619b0e92f8402c5f577
Signed-off-by: Dragan Cecavac <dragan.cecavac@imgtec.com>

arch/mips/Kconfig

@@ -254,7 +254,7 @@ config MACH_JZ4740
 
 config MACH_JZ4780
 	bool "Ingenic JZ4780 based machines"
-	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select SYS_SUPPORTS_ZBOOT_UART16550
@@ -271,8 +271,8 @@ config MACH_JZ4780
 	select BUILTIN_DTB
 	select USE_OF
 	select LIBFDT
-	select MIPS_CPU_SCACHE
 	select SYS_SUPPORTS_SMP
+	select CONFIG_XBURST_CACHE
 
 config LANTIQ
 	bool "Lantiq based platforms"
@@ -1967,7 +1967,11 @@ config CPU_R4K_FPU
 
 config CPU_R4K_CACHE_TLB
 	bool
-	default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+	default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON || MACH_JZ4780)
+
+config XBURST_CACHE
+	bool
+	default y if (MACH_JZ4780)
 
 config MIPS_MT_SMP
 	bool "MIPS MT SMP support (1 TC on each available VPE)"

arch/mips/Makefile

@@ -62,7 +62,7 @@ ld-emul			= $(32bit-emul)
 vmlinux-32		= vmlinux
 vmlinux-64		= vmlinux.64
 
-cflags-y		+= -mabi=32
+cflags-y		+= -mabi=32 -mgp32 -mfp32
 endif
 
 ifdef CONFIG_64BIT
@@ -88,7 +88,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 # crossformat linking we rely on the elf2ecoff tool for format conversion.
 #
 cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe
-cflags-y			+= -msoft-float
+cflags-y			+= -msoft-float -Wa,-mhard-float
 LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls

arch/mips/boot/dts/jz4780.dtsi

@@ -598,6 +598,8 @@
 			clocks = <&cgu JZ4780_CLK_SADC>;
 			clock-names = "adc";
 		};
+
+
 	};
 
 	ahb2 {
@@ -772,5 +774,25 @@
 			phy-names = "usb2-phy";
 			g-tx-fifo-size = <256 256 256 256>;
 		};
+		vpu: jz4780-vpuk@0x13200000 {
+			compatible = "ingenic,jz4780-vpu";
+			reg = <0x13200000 0x100000>;
+
+			 clocks = <&cgu JZ4780_CLK_VPU>;
+			 clock-names = "vpu_clk";
+
+			 interrupt-parent = <&intc>;
+			 interrupts = <62>;
+		};
+		ipu: jz4780-ipu0@0x13080000 {
+			compatible = "ingenic,jz4780-ipu0";
+			reg = <0x130b0000 0x800>;
+
+			 clocks = <&cgu JZ4780_CLK_IPU>;
+			 clock-names = "ipu_clk";
+
+			 interrupt-parent = <&intc>;
+			 interrupts = <22>;
+		};
 	};
 };

arch/mips/include/asm/cpu-features.h

@@ -13,6 +13,10 @@
 #include <asm/cpu-info.h>
 #include <cpu-feature-overrides.h>
 
+//#ifndef current_cpu_type
+//#define current_cpu_type()      current_cpu_data.cputype
+//#endif
+
 /*
  * SMP assumption: Options of CPU 0 are a superset of all processors.
  * This is true for all known MIPS systems.
@@ -107,6 +111,9 @@
 #ifndef kernel_uses_llsc
 #define kernel_uses_llsc	cpu_has_llsc
 #endif
+#ifndef cpu_has_mmips
+#define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
+#endif
 #ifndef cpu_has_mips16
 #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
@@ -259,10 +266,18 @@
 #define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif
 
+#ifndef cpu_has_mxu
+#define cpu_has_mxu		(cpu_data[0].ases & MIPS_ASE_XBURSTMXU)
+#endif
+
 #ifndef cpu_has_userlocal
 #define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
 #endif
 
+#ifndef cpu_has_contextconfig
+#define cpu_has_contextconfig	((cpu_data[0].options & MIPS_CPU_CTXTC) || cpu_has_smartmips)
+#endif
+
 #ifdef CONFIG_32BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)

arch/mips/include/asm/cpu.h

@@ -382,5 +382,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
 #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
 #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
+#define MIPS_ASE_XBURSTMXU	0x80000000 /* CPU supports MIPS MT */
 
 #endif /* _ASM_CPU_H */

arch/mips/include/asm/mach-jz4740/jz4780/cpu-feature-overrides.h

@@ -34,7 +34,7 @@
 #define cpu_has_ic_fills_f_dc	0
 #define cpu_has_pindexed_dcache 0
 #define cpu_has_mips32r1	1
-#define cpu_has_mips32r2	1
+#define cpu_has_mips32r2	0
 #define cpu_has_mips64r1	0
 #define cpu_has_mips64r2	0
 #define cpu_has_dsp		0

arch/mips/include/asm/mxu.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2005 Mips Technologies
+ * Author: Chris Dearman, chris@mips.com derived from fpu.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_MXU_H
+#define _ASM_MXU_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+#include <asm/mxu_media.h>
+
+static inline void __init_mxu(void)
+{
+	register unsigned int val asm("t0");
+	val = 3;
+	asm volatile(".word	0x7008042f \n\t"::"r"(val));
+}
+
+void __save_mxu(void *);
+void __restore_mxu(void * tsk_void);
+
+static inline void init_mxu(void)
+{
+	if(cpu_has_mxu)
+		__init_mxu();
+}
+
+
+#define save_mxu(tsk)							\
+	do {										\
+		if (cpu_has_mxu)						\
+			__save_mxu(tsk);					\
+	} while (0)
+
+#define restore_mxu(tsk)						\
+	do {										\
+		if (cpu_has_mxu)						\
+			__restore_mxu(tsk);					\
+	} while (0)
+
+#define __get_mxu_regs(tsk)						\
+	({											\
+		if (tsk == current)						\
+			__save_mxu(current);				\
+												\
+		tsk->thread.mxu.regs;					\
+	})
+
+#define __let_mxu_regs(tsk,regs)				\
+	do{											\
+		int i;									\
+		for(i = 0; i < NUM_MXU_REGS;i++)		\
+			tsk->thread.mxu.regs[i] = regs[i];	\
+		if (tsk == current)						\
+			__save_mxu(current);				\
+	}while(0)
+
+#endif /* _ASM_MXU_H */