Discussion on methods of debugging FIM

The FIM is a combination of FIU, FME and Port designs.

Initially, the FIU and Port designs are debugged on real hardware on a PC with a FPGA add-on card. The PCIe and AXI-lite transactions are captured with in-system JTAG probes(System ILA). The DFL RAMs in the FIU and AFU are updated with JTAG-AXI master to satisfy the requirements of the OPAE driver.

Later on, both the FIU and Port designs are verified in simulation, which is provided in ./hw/prj/fim/, with a PCIe Root Complex BFM. However, this RTL-oriented sub-system simulation is limited by the capability of the test cases that are manually created.

Only a full-system co-simulation can verify the entire data-path and interactions from application and driver running on PC down to accelerator residing in FPGA. Fortunately, I found this wonderful work. And I am working on setting up a full-system co-simulation of OPAE on QEMU and FIM on Vivado XSim.(11282019, Thanksgiving Day)

The original demo code is thoroughly studied and successfully ported to my development environment: Ubuntu18.04, Vivado2018.3, XSim and KCU105. The modified demo code with a verified installation flow is hosted on Github.(12122019, Double Twelve Day)