Create port on pin enhancement (#3858)

* edb intersection bug fix

* create port on pin -> port name option added

pyaedt/edb_core/components.py

@@ -713,7 +713,7 @@ def create_source_on_component(self, sources=None):
         return True
 
     @pyaedt_function_handler()
-    def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0):
+    def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0, port_name=None):
         """Create circuit port between pins and reference ones.
 
         Parameters
@@ -732,6 +732,8 @@ def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0):
             str, [str], EDBPadstackInstance, [EDBPadstackInstance]
         impedance : Port impedance
             str, float
+        port_name : Port Name (Optional) when provided will overwrite the default naming convention
+            str
 
         Returns
         -------
@@ -767,6 +769,8 @@ def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0):
         if not len([pin for pin in pins if isinstance(pin, EDBPadstackInstance)]) == len(pins):
             self._logger.error("Pin list must contain only pins instances")
             return
+        if not port_name:
+            port_name = "Port_{}_{}".format(pins[0].net_name, pins[0].name)
         if len([pin for pin in reference_pins if isinstance(pin, str)]) == len(reference_pins):
             ref_cmp_pins = []
             for ref_pin_name in reference_pins:
@@ -781,17 +785,17 @@ def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0):
         if len(pins) > 1:
             group_name = "group_{}_{}".format(pins[0].net_name, pins[0].name)
             pin_group = self.create_pingroup_from_pins(pins, group_name)
-            term = self._create_pin_group_terminal(pingroup=pin_group)
+            term = self._create_pin_group_terminal(pingroup=pin_group, term_name=port_name)
 
         else:
-            term = self._create_terminal(pins[0])
+            term = self._create_terminal(pins[0], term_name=port_name)
         term.SetIsCircuitPort(True)
         if len(reference_pins) > 1:
             ref_group_name = "group_{}_{}_ref".format(reference_pins[0].net_name, reference_pins[0].name)
             ref_pin_group = self.create_pingroup_from_pins(reference_pins, ref_group_name)
-            ref_term = self._create_pin_group_terminal(pingroup=ref_pin_group)
+            ref_term = self._create_pin_group_terminal(pingroup=ref_pin_group, term_name=port_name + "_ref")
         else:
-            ref_term = self._create_terminal(reference_pins[0])
+            ref_term = self._create_terminal(reference_pins[0], term_name=port_name + "_ref")
         ref_term.SetIsCircuitPort(True)
         term.SetImpedance(self._edb.utility.value(impedance))
         term.SetReferenceTerminal(ref_term)
@@ -820,7 +824,7 @@ def create_port_on_component(
             False will take the closest reference pin and generate one port per signal pin.
         refnet : string or list of string.
             list of the reference net.
-        port_name : string
+        port_name : str
             Port name for overwriting the default port-naming convention,
             which is ``[component][net][pin]``. The port name must be unique.
             If a port with the specified name already exists, the
@@ -933,13 +937,16 @@ def create_port_on_component(
         return True
 
     @pyaedt_function_handler()
-    def _create_terminal(self, pin):
+    def _create_terminal(self, pin, term_name=None):
         """Create terminal on component pin.
 
         Parameters
         ----------
         pin : Edb padstack instance.
 
+        term_name : Terminal name (Optional).
+            str.
+
         Returns
         -------
         Edb terminal.
@@ -951,7 +958,8 @@ def _create_terminal(self, pin):
         cmp_name = pin.GetComponent().GetName()
         net_name = pin.GetNet().GetName()
         pin_name = pin.GetName()
-        term_name = "{}.{}.{}".format(cmp_name, pin_name, net_name)
+        if term_name is None:
+            term_name = "{}.{}.{}".format(cmp_name, pin_name, net_name)
         for term in list(self._pedb.active_layout.Terminals):
             if term.GetName() == term_name:
                 return term
@@ -1223,7 +1231,7 @@ def add_rlc_boundary(self, component=None, circuit_type=True):
             return True
 
     @pyaedt_function_handler()
-    def _create_pin_group_terminal(self, pingroup, isref=False):
+    def _create_pin_group_terminal(self, pingroup, isref=False, term_name=None):
         """Creates an EDB pin group terminal from a given EDB pin group.
 
         Parameters
@@ -1232,14 +1240,16 @@ def _create_pin_group_terminal(self, pingroup, isref=False):
 
         isref : bool
 
+        term_name : Terminal name (Optional). If not provided default name is Component name, Pin name, Net name.
+            str.
+
         Returns
         -------
         Edb pin group terminal.
         """
         pin = list(pingroup.GetPins())[0]
-        term_name = "{}.{}.{}".format(
-            pin.GetComponent().GetName(), pin.GetComponent().GetName(), pin.GetNet().GetName()
-        )
+        if term_name is None:
+            term_name = "{}.{}.{}".format(pin.GetComponent().GetName(), pin.GetName(), pin.GetNet().GetName())
         for t in list(self._pedb.active_layout.Terminals):
             if t.GetName() == term_name:
                 return t