verilog-codes-

mini projects This Repository consists of various mini projects i came across while learning HDL languages.

Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
1010 sequence detector using mealy FSM		1010 sequence detector using mealy FSM
ripple up counter 0 to 7		ripple up counter 0 to 7
sequence detector		sequence detector
1bitadd.v		1bitadd.v
Alu.v		Alu.v
README.md		README.md
decoder.v		decoder.v
dlatch.v		dlatch.v
fulladder.sv		fulladder.sv
half subtractor.v		half subtractor.v
hello.v		hello.v
hello_tb.v		hello_tb.v
inheritance.sv		inheritance.sv
mlkqbusvytc		mlkqbusvytc
priencoder.v		priencoder.v
randomization.sv		randomization.sv
sr_latch.v		sr_latch.v
updowncounter.v		updowncounter.v
vlsi.txt		vlsi.txt
washingmachine.v		washingmachine.v

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