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IP Request: PCIE Gen2 EndPoint #47

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chili-chips-ba opened this issue Dec 7, 2024 · 0 comments

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chili-chips-ba commented Dec 7, 2024

@pu-cc input from today's meeting:

Most customers are looking for PCIE Gen2 EP functionality
GateMate SerDes is very similar to Xilinx GTP. We need PIPE interface wrapper for it

@chili-chips-ba input:

But, Xilinx also comes with PCIE HM for L2 and L3 functions. Where do we get it from for GateMate?
Even if we have RTL for it, how much space will it take? What will be left for the customer logic if PCIE EP function takes the most of the GateMate 20K LUTs?
Hence the question for @pu-cc:

Please list the most frequently asked-for application of the PCIE Gen2 EndPoint, including the number of lanes.

chili-chips-ba self-assigned this

chili-chips-ba added the Phase2 label

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