Skip to content

Issues: chili-chips-ba/openCologne

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

33 Open 34 Closed
33 Open 34 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

CPE usage report when routing fails enhancement New feature or request
#67 opened Mar 10, 2025 by tarik-ibrahimovic
@pu-cc
Yosys LUT primitives translation into CC primitives -- potentially underperforming? benchmarking Real-life testcase for assessment of efficiency, performance, and beyond
#66 opened Mar 6, 2025 by tarik-ibrahimovic
@pu-cc @tarik-ibrahimovic
Pre-built yosys doesn't support tcl scripts enhancement New feature or request
#65 opened Mar 5, 2025 by tarik-ibrahimovic
@pu-cc
2
Yosys netlist is severly affected by non-synthesizable construct! benchmarking Real-life testcase for assessment of efficiency, performance, and beyond bug Something isn't working
#64 opened Mar 2, 2025 by tarik-ibrahimovic
@pu-cc @chili-chips-ba
3
Is there an option for modular (as opposed to flat) implementation flow for GateMate?! enhancement New feature or request question Further information is requested
#63 opened Mar 1, 2025 by tarik-ibrahimovic
@pu-cc
1
Unexpected Fmax sensitivity in fpga_torture benchmarking Real-life testcase for assessment of efficiency, performance, and beyond help wanted Extra attention is needed
#62 opened Mar 1, 2025 by tarik-ibrahimovic
@pu-cc @chili-chips-ba @tarik-ibrahimovic
3
Corescore testing mismatch in simulation and hardware help wanted Extra attention is needed
#61 opened Mar 1, 2025 by tarik-ibrahimovic
@pu-cc @chili-chips-ba @tarik-ibrahimovic
Post-implementation simulation of block RAMs help wanted Extra attention is needed
#60 opened Mar 1, 2025 by tarik-ibrahimovic
@pu-cc @tarik-ibrahimovic
Clarification on timing p_r option results help wanted Extra attention is needed
#59 opened Mar 1, 2025 by tarik-ibrahimovic
@pu-cc @tarik-ibrahimovic
3
Evaluation of Pros and Cons of GateMate 4-input Multiplexer over traditional 4-Input LUTs benchmarking Real-life testcase for assessment of efficiency, performance, and beyond
#58 opened Feb 27, 2025 by PythonLinks
@pu-cc @chili-chips-ba @tarik-ibrahimovic
Multiplexer Stress Test help wanted Extra attention is needed question Further information is requested
#57 opened Feb 21, 2025 by PythonLinks
@pu-cc @PythonLinks
@chili-chips-ba @tarik-ibrahimovic @nsokolovic7
28
Math Stress Test enhancement New feature or request help wanted Extra attention is needed
#56 opened Feb 20, 2025 by PythonLinks
@pu-cc @PythonLinks @chili-chips-ba
2
LUTRAM stress test underutilization question Further information is requested
#52 opened Feb 14, 2025 by tarik-ibrahimovic
@pu-cc
Installation Error good first issue Good for newcomers
#50 opened Dec 21, 2024 by udge2022
@pu-cc @tarik-hamedovic
5
One and only EU
#49 opened Dec 12, 2024 by goran-mahovlic
@pu-cc @chili-chips-ba
2
PCB PMOD Request: Olimex connector to MikroBus (mbusIO) Assembled Board is assembled PCB request Proposal for new PCB designs
#48 opened Dec 7, 2024 by goran-mahovlic
@goran-mahovlic
IP Request: PCIE Gen2 EndPoint Phase2 For ideas and proposals to consider in the next funding round.
#47 opened Dec 7, 2024 by chili-chips-ba
@chili-chips-ba
PCB PMOD Request: Olimex connector to dual DVI-IN/DVI-OUT (ddvIO) Assembled Board is assembled PCB request Proposal for new PCB designs Phase2 For ideas and proposals to consider in the next funding round.
#46 opened Dec 5, 2024 by goran-mahovlic
@goran-mahovlic
1
PCB PMOD Request: Olimex extension template enhancement New feature or request PCB request Proposal for new PCB designs
#45 opened Dec 2, 2024 by goran-mahovlic
@goran-mahovlic @tarik-hamedovic
2
PCB PMOD Request: Olimex connector to dual PMOD (pdbIO) PCB request Proposal for new PCB designs
#44 opened Nov 29, 2024 by goran-mahovlic
@goran-mahovlic
3
PCB PMOD Request: USB2.0 PHY (usbIO) Assembled Board is assembled PCB request Proposal for new PCB designs
#43 opened Nov 3, 2024 by chili-chips-ba
@goran-mahovlic
10
PCB PMOD Request: An array of Power Transistors (pwrIO) Assembled Board is assembled PCB request Proposal for new PCB designs
#42 opened Nov 3, 2024 by chili-chips-ba
@goran-mahovlic @aimamovic6
14
PCB PMOD Request: Realtime clock with PWR switch (tmrIO) Assembled Board is assembled PCB request Proposal for new PCB designs
#40 opened Nov 3, 2024 by chili-chips-ba
@goran-mahovlic
12
Constraints-driven P_R?! question Further information is requested
#38 opened Sep 27, 2024 by chili-chips-ba
@pu-cc
L2T4 logic funcion gaps compared to standard LUT4?! question Further information is requested
#37 opened Sep 27, 2024 by chili-chips-ba
@pu-cc
7
ProTip! Adding no:label will show everything without a label.