Yosys netlist is severly affected by non-synthesizable construct!

[tarik-ibrahimovic]

Removing the $display line from this excerpt completely changes the synth netlist. The changes are so significant that the pnr fails to route 2 cores for the latter case, in 1.corescore test (decreasing the number of cores from 56 to 54).

serving_ram.v file version 1.0.2 from serv repository

   initial
     if(|memfile) begin
	$display("Preloading %m from %s", memfile);
	$readmemh(memfile, mem);
     end

[tarik-ibrahimovic]

This is a known issue in Yosys, as documented in issue #4925. Chaotic behavior has been observed, and using different seed values may sometimes yield better results. The variation amounts to approximately ±2 cores—about 5% of the total. When combined with the netlist translation performed by p_r, this issue may further exacerbate the overall unreliability of the results.

[pu-cc]

May I ask in advance why you are removing the display? P&R should actually ignore any initial blocks in the netlists.

[tarik-ibrahimovic]

Removing the display isn't necessary anymore, since this issue has been resolved.